Datasheet

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UDG−04091
C9
0.1 µF
R12 10 Ω
R16 10 kΩ
R8 10 kΩ
R5 33.2 kΩ
C6
0.1 µF
R22
10 Ω
C2
0.1 µF
V
OUT
R13
10 kΩ
V
OUT
C1
0.1 µF
1.0 Ω
R21 51 Ω
R20 51 Ω
1.0 Ω
R10
10 kΩ
R14
10 kΩ
1
2
3
4
30
29
28
27
PGND
LDRV2
SW2
HDRV2
LDRV1
VIN5
SW1
HDRV1
TPS40130DBT
5
6
7
8
BOOT1
OVSET
VOUT
GSNS
9
10
11
DIFFO
CS1
CSRT1
12
13
14
15
COMP
VREF
DROOP
FB
26
25
24
23
BOOT2
SS
UVLO
BP5
22
21
20
19
AGND
CS2
CSRT2
RT
18
17
16
PGOOD
ILIM
EN/SYNC
R17
R18
5 V
VREF
R6
R7
5 V
C7 2200 pF
L2
R1C4
D1
BAT54A
D2
5 V
L1
R2 C5
5 V
5 V
DIFFO
R11C8
C17 C15
Q2
Q5,
Q6
PGND
C20
C19
C21 C12C13
Q1
Q3,
Q4
PGND
C10
FB
R19
EN/SYNC
5 V
LOAD
V
OUT
TPS40130
SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION (continued)
Figure 17 shows the configuration for efficiently operating at high frequencies. With the power stages input at 5
V, the switching losses in the upper MOSFET are significantly reduced. The upper MOSFET should be selected
for lower R
DS(on)
because the conduction losses are somewhat higher at the higher duty cycle.
Figure 17. Application Circuit For High-Frequency Operation With Input Voltage of 5 V
25
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