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Additional Application Circuits
1
2
3
4
30
29
28
27
PGND
LDRV2
SW2
HDRV2
LDRV1
VIN5
SW1
HDRV1
TPS40130DBT
5
6
7
8
BOOT1
OVSET
VOUT
GSNS
9
10
11
DIFFO
CS1
CSRT1
12
13
14
15
COMP
VREF
DROOP
FB
26
25
24
23
BOOT2
SS
UVLO
BP5
22
21
20
19
AGND
CS2
CSRT2
RT
18
17
16
PGOOD
ILIM
EN/SYNC
R17
R18
5 V
R6
R7
12 V
C7 2200 pF
L2
R1C4
D1
BAT54A
D2
5 V
L1
R2 C5
12 V
12 V
R11C8
C17 C15
Q2
Q5,
Q6
PGND
C20
C19
C21 C12C13
Q1
Q3,
Q4
PGND
C10
FB
EN/SYNC
5 V
BP5
SS
8
1
2
3
14
9
10
12
VCC
FB
BIAS
NCPU1
VOUT
VID5
VID0
VID1
4
5
6
7
VID2
VID3
VID4
GND
13NCPU2
TPS40120
11N/C
DIFFO
UDG−04088
C9
0.1 µF
R12 10 Ω
R16 10 kΩ
R8 10 kΩ
R5 90.9 kΩ
C6
0.1 µF
R22
10 Ω
C2
0.1 µF
V
OUT
R13
10 kΩ
R14
10 kΩ
V
OUT
C1
0.1 µF
1.0 Ω
R21 51 Ω
R20 51 Ω
1.0 Ω
V
REF
TPS40130
SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION (continued)
Figure 14 shows a VRM10.x compliant solution where the output voltage is controlled by the VID code of the
TPS40120. The six-bit controller provides outputs from 0.8375 V to 1.600 V in 12.5 mV steps for VRM 10.x or
provides five-bit control for other Intel processors. When the TPS40120 receives a VID of x11111, indicating the
no CPU state, output NCPU1# pulls the soft-start (SS) pin low insuring the output voltage soft-starts with a valid
VID code.
Figure 14. Application Circuit with VID Control
Figure 15 shows the configuration with the TPS40130 processing power from two different input power sources,
12 V and 5 V is shown. This is useful when there is not sufficient power from a single input source to provide the
required output power. The inductor currents are not equal and the difference in the peak currents are
approximately:
22
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