Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers TSSOP 30

www.ti.com

FEATURES APPLICATIONS

DESCRIPTION

LDRV1

VIN5

SW1

HDRV1

BOOT1

OVSET

VOUT

GSNS

DIFFO

CS1

CSRT1

COMP

VREF

DROOP

PGND

LDRV2

SW2

HDRV2

BOOT2

UVLO

BP5

AGND

CS2

CSRT2

PGOOD

ILIM

EN/SYNC

DBT PACKAGE

(TOP VIEW)

RHB PACKAGE

(TOP VIEW)

32 31 30 29 28 27 26 25

9 10 11 12 13 15 16

BOOT1

OVSET

VOUT

GSNS

DIFFO

CS1

CSRT1

BOOT2

UVLO

BP5

AGND

CS2

CSRT2

COMP

HDRV1

SW1

VIN5

LDRV1

PGND

LDRV2

SW2

HDRV2

VREF

DROOP

EN/SYNC

ILIM

PGOOD

TPS40130

SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005

TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER WITH INTEGRATED MOSFET

DRIVERS

• Graphic Cards

• Two-Phase Interleaved Operation

• Internet Servers

• 3-V to 40-V Power Stage Operation Range

• Networking Equipment

• Supports Up to 6-V V

OUT

With External Divider

• Telecommunications Equipment

• Requires VIN5 @ 50 mA, Typical, Depending

• DC Power Distributed Systems

on External MOSFETs and Switching

Frequency

• 1-µA Shutdown Current

The TPS40130 is a two-phase synchronous buck

• Programmable Switching Frequency up to 1

controller that is optimized for low-output voltage,

MHz/Phase

high-output current applications powered from a

• Current Mode Control with Forced Current

supply between 3 V and 40 V. A multi-phase

Sharing

converter offers several advantages over a single

power stage including lower current ripple on the

• Better than 1% Internal 0.7-V Reference

input and output capacitors, faster transient response

• Resistive Divider Sets Direct Output Over

to load steps, improved power handling capabilities,

Voltage Threshold and Sets Input

and higher system efficiency.

Undervoltage Lockout

Each phase can be operated at a switching

• True Remote Sensing Differential Amplifier

frequency up to 1 MHz, resulting in an effective

• Resistive or Inductor’s DCR Current Sensing

ripple frequency of up to 2 MHz at the input and the

• 30-pin TSSOP or 32-Pin QFN Packages

output. The two phases operates 180 degrees

out-of-phase.

• Can Be Used with TPS40120 to Provide a 6-Bit

Digitally Controlled Output

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

PAGE 1
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER WITH INTEGRATED MOSFET DRIVERS FEATURES APPLICATIONS • • • • • • • • • Each phase can be operated at a switching frequency up to 1 MHz, resulting in an effective ripple frequency of up to 2 MHz at the input and the output. The two phases operates 180 degrees out-of-phase.
PAGE 2
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 ORDERING INFORMATION TA -40°C to 85°C (1) (2) (3) PACKAGE PART NUMBER Plastic TSSOP(DBT) (1) TPS40130DBT (2) (3) Plastic QFN (RHB) TPS40130RHB The DBTpackage is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40130DBTR). The TPS40130DBTRG4 is a lead (Pb) free product, which means that it is compatible with current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.
PAGE 4
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.5 5.0 5.5 1 5 µA 0.5 1.0 1.5 mA 4.3 5.0 5.5 2 3 5 4.00 4.25 4.
PAGE 5
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.5 5.0 6.5 µA 0.95 1.00 1.05 V -5 4 10 mV 5.1 5.6 6.
PAGE 6
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.4 0.5 0.6 UNIT RAMP Ramp amplitude (3) Ramp valley (3) 1.4 V POWER GOOD PGOOD high threshold VFB relative to VREF 10% 14% PGOOD low threshold VFB relative to VREF -14% -10% VOL Low-level output voltage IPGOOD = 4 mA ILEAK PGOOD bias current VPGOOD = 5.
PAGE 7
TPS40130 www.ti.
PAGE 8
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 Terminal Functions (continued) TERMINAL NAME 8 I/O NO. DESCRIPTION RHB DBT FB 12 15 I Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal reference level of 700 mV. This pin is also used for the PGOOD and undervoltage comparators. GSNS 4 8 I Inverting input of the differential amplifier. This pin should be connected to ground at the point of load.
PAGE 9
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL BLOCK DIAGRAM BP5 23 AGND 22 CS1 10 CSRT1 11 VOUT 7 TPS40130DBT U1 + 20 kΩ U7 20 kΩ + 5 BOOT1 4 HDRV1 3 SW1 2 VIN5 1 LDRV1 30 PGND 26 BOOT2 27 HDRV2 28 SW2 29 LDRV2 18 PGOOD 20 kΩ GSNS 8 U6 20 kΩ DIFFO 13 Ramp1 U2 0.
PAGE 10
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL DESCRIPTION (continued) Startup Sequence Figure 1 shows a typical start up with the VIN5 and BP5 applied to the controller and then the EN/SYNC being enabled. Shut down occurs when the VIN5 is removed VIN5 BP5 EN/SYNC 1.0V 0.7V SS SSWAIT VOUT PGOOD POR UDG−04031 Figure 1.
PAGE 11
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL DESCRIPTION (continued) Current Sensing and Balancing (U1, U9 and U18) The controller employs peak current mode control scheme, thus naturally provides certain degree of current balancing. With current mode, the level of current feedback should comply with certain guidelines depending on duty factor known as “slope compensation” to avoid the sub-harmonic instability.
PAGE 12
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL DESCRIPTION (continued) C A + 100 ns RA (2) Even though CA may calculate to less than 1 pF, a capacitance of no more than 4.7 pF is recommended. Soft-Start A capacitor connected to the soft start pin (SS) sets the power-up time. When EN is high and POR is cleared, the calibrated current source, U13, starts charging the external soft start capacitor. The PGOOD pin is held low during the start up.
PAGE 13
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL DESCRIPTION (continued) After the device is enabled and prior to the IC starting (during the first 32 clock cycles), a 5-µA current flows out of the CS1 and CS2 pins. The current flows through the external components: current sense resistor, RCS, the output inductor and the output capacitor(s) to ground. If the voltage on the CS1 and CS2 pins exceed 0.
PAGE 14
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 Setting the Switching Frequency The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground. See Equation 6. R T + 0.8 ƪǒ 36 Ǔ ƫ 103 * 9 f PH (6) fPH is a single phase frequency, kHz. The RT resistor value is expressed in kΩ. See Figure 4. 500 RT − Timing Resistance − kΩ 450 400 350 300 250 200 150 100 50 0 0 200 400 600 800 1000 fSW − Phase Switching Frequency − kHz Figure 4.
PAGE 15
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 Setting Overcurrent Protection Setting the overcurrent protection is given in the following equations. Care must be taken when calculating VILIM to include the increase in RCS caused by the output current as it approaches the overcurrent trip point. The DCR (RCS in the equation) of the inductor increases approximately 0.39% per degree Centigrade. V ILIM + 2.
PAGE 16
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 VOUT TPS40130DBT DIFFO 7 + 9 GSNS 8 COMP 12 C1 R1 C2 R2 FB 15 Modulator DROOP LOUT + 14 VOUT COUT RBIAS ROUT 13 VREF + VREF RESR UDG−04029 Figure 5. Compensation Components The following expressions help in choosing components of the EA compensation network. It is recommended to fix value of the resistor R1 first as it further simplifies adjustments of the output voltage without altering the compensation network.
PAGE 17
TPS40130 www.ti.
PAGE 18
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 C2 + C1 2p R2 C1 ǒf DROOPZ * 1 Ǔ (21) When attempting closing the feedback loop at frequency that is close to the theoretical limit, use the above considerations as a first approximation and perform on bench measurements of closed loop parameters as effects of switching frequency proximity and finite bandwidth of voltage and current amplifiers may substantially alter them as it is shown in Figure 8.
PAGE 19
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 TPS40130DBT OVSET 6 GSNS Differential Amplifier 8 VOUT 7 + DIFFO 9 R2 R3 C1 COMP 12 R1 Error Amplifier FB 15 + DROOP R4 RBIAS VIN 14 VREF RDROOP IDROOP 13 R5 ILIM 17 R6 R7 UVLO 24 + R8 700 mV UDG−04032 Figure 9. Implementing the Droop Function, Resistor Between DROOP and VREF. VOUT − Output Voltage − V VOUT VDROOP IOUT(max) 0 IOUT − Output Current − A UDG−03116 Figure 10.
PAGE 20
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 Inductor DCR Current Sense Inductor DCR current sensing is a known lossless technique to retrieve current proportional signal. Referring to Figure 11. At any given frequency the DCR voltage can be calculated using Equation 23 and Equation 24.
PAGE 21
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION Applications Circuit Figure 13 shows a typical applications circuit providing 1.5 VOUT at 40 A. VOUT R2 C5 C4 R1 C19 L1 L2 12 V 12 V 5V C1 0.1 µF Q1 D1 BAT54A C13 C21 C12 C20 C2 0.1 µF D2 Q3, Q4 C17 C15 Q2 TPS40130DBT 1.0 Ω 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 1.
PAGE 22
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) Additional Application Circuits Figure 14 shows a VRM10.x compliant solution where the output voltage is controlled by the VID code of the TPS40120. The six-bit controller provides outputs from 0.8375 V to 1.600 V in 12.5 mV steps for VRM 10.x or provides five-bit control for other Intel processors.
PAGE 23
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) (D1 * D2) DI PEAK ^ 0.067 DCR h (26) where • D1 is the duty cycle for VIN1 • D2 is the duty cycle for VIN2 • DCR is the resistance of the output inductor • η is the efficiency of the converter VOUT R2 C5 C4 R1 C19 L1 L2 12 V 5V 5V Q1 C1 0.1 µF D1 BAT54A C13 C21 C12 C20 C2 0.1 µF D2 Q3, Q4 Q2 C15 TPS40130DBT 1.0 Ω 1 LDRV1 PGND 30 1.
PAGE 24
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) Figure 16 shows the required 5-V input being generated with an external linear regulator. The regulator shown is the TL431 shunt regulator which is a very cost effective solution. Depending on the required current to the MOSFET gates, the 115 Ω resistor may need to be a ¼ W or ½ W resistor.
PAGE 25
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) Figure 17 shows the configuration for efficiently operating at high frequencies. With the power stages input at 5 V, the switching losses in the upper MOSFET are significantly reduced. The upper MOSFET should be selected for lower RDS(on) because the conduction losses are somewhat higher at the higher duty cycle. VOUT R2 C5 C4 R1 C19 L1 L2 5V 5V 5V Q1 C1 0.
PAGE 26
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION (continued) Figure 18 shows how to configure for a 5-V output. The resistor dividers on the CSx and CSRTx inputs are necessary to reduce the common mode voltage into the current sense amplifiers. The differential amplifier is not used because with a 5-V output, remote sensing is not generally necessary.
PAGE 27
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTRICS VDIFFOUT (50 mV/div) VDIFFOUT (50 mV/div) IL1 (5 A / div) IL1, IL2 (5 A/div) IL2 (5 A / div) VSW2 (10 V / div) VSW2 (10 V / div) t − Time − 20 µs/div t − Time − 4 µs/div Figure 19. Load Transient Figure 20.
PAGE 28
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTRICS (continued) VDIFFOUT (500 mV/div) VEN/SYNC (5 V/div) VSS (500 mV / div) VEN/SYNC (5 V / div) VHDRV1 (10 V / div) VHDRV2 (10 V / div) t − Time − 400 µs/div t − Time − 400 ns/div Figure 23. Start-Up with EN/SYNC VEN/SYNC (5 V/div) Figure 24.
PAGE 29
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTRICS (continued) VFB (200 mV / div) VFB (200 mV/ div) VSS (1 V/ div) VSS (1 V/div) IL2, IL2 (10 A / div) IL2, IL2 (10 A / div) VFB = 0.588 V t − Time − 40 µs/div t − Time − 4 ms/div Figure 27. Overcurrent, Hiccup Mode Figure 28. Overcurrent LAYOUT CONSIDERATIONS Introduction Any pin number references are for the DBT, TSSOP package.
PAGE 30
TPS40130 www.ti.com SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 LAYOUT CONSIDERATIONS (continued) Routing The traces that connect to C5 and C4 should be made directly at the capacitor(s) and routed on an internal signal plane to CS1, CSRT1 and CS2, CSRT2, respectively. In addition, a small value of R-C filter may be used on the CSx and CSRTx lines, with these components placed close to the device. A 5.
PAGE 31
PACKAGE OPTION ADDENDUM www.ti.
PAGE 32
PACKAGE OPTION ADDENDUM www.ti.com (4) 27-Jul-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 33
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40130DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS40130RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS40130RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 34
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40130DBTR TSSOP DBT 30 2000 367.0 367.0 38.0 TPS40130RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TPS40130RHBT VQFN RHB 32 250 210.0 185.0 35.
PAGE 35
PAGE 36
PAGE 37
PAGE 38
PAGE 39
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.