Datasheet

www.ti.com
TPS40100
SLUS601–MAY 2005
ELECTRICAL CHARACTERISTICS (continued)
-40°C ≤ T
A
=T
J
≤ 85°C, V
VDD
=12V,R
RT
= 182 kΩ,R
GM
= 232 kΩ,R
ILIM
= 121 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE MARGINING
Feedback voltage margin 5% up V
MGU
≤ 500 mV 715 725 735
V
FBMGU
mV
Feedback voltage margin 3% up 2 V ≤ V
MGU
≤ 3 V 700 711 720
I
MGUP
Margin-up bias current 60 80 100 µA
Feedback voltage margin 5% down V
MGD
≤ 500 mV 645 655 665
V
FBMGD
mA
Feedback voltage margin 3% down 2 V ≤ V
MGD
≤ 3 V 660 669 680
I
MGDN
Margin-down bias current 60 80 100 µA
t
MGDLY
Margining delay time
(3)
12 30
ms
t
MGTRAN
Margining transition time 1.5 7.0
CURRENT SENSE AMPLIFIER
gm
CSA
Current sense amplifier gain T
J
=25°C 300 333 365 µS
TC
GM
Amplifier gain temperature coefficient -2000 ppm/°C
V
GMLIN
Gm linear range voltage T
J
=25°C -50 50 mV
I
ISNS
Bias current at ISNS pin V
VO
=V
ISNS
= 3.3 V 250 nA
06
V
GMCM
Input voltage common mode V
4.5 V ≤ V
IN
≤ 5.5 V 0 3.6
CURRENT LIMIT
V
ILIM
ILIM pin voltage to trip overcurrent 1.44 1.48 1.52 V
t
ILIMDLY
Current limit comparator propagation delay HDRV transition from on to off 70 140 ns
DRIVER SPECIFICATIONS
t
RHDRV
HIgh-side driver rise time
(4)
C
LOAD
= 4.7 nF 57
ns
t
FHDRV
HIgh-side driver fall time
(4)
C
LOAD
= 4.7 nF 47
I
HDRVSRPKS
HIgh-side driver peak source current
(4)
800
mA
I
HDRVSRMIL
HIgh-side driver source current at 2.5 V
(4)
V
HDRV
-V
SW
= 2.5 V 700
I
HSDVSNPK
HIgh-side driver peak sink current
(4)
1.3
A
I
HDRVSNMIL
High-side driver sink current at 2.5 V
(4)
V
HDRV
-V
SW
= 2.5 V 1.2
R
HDRVUP
HIgh-side driver pullup resistance I
HDRV
= 300 mA 2.4 4.0
Ω
R
HDRVDN
HIgh-side driver pulldown resistance I
HDRV
= 300 mA 1.0 1.8
t
RLDRV
Low-side driver rise time
(4)
C
LOAD
= 4.7 nF 57
ns
t
FLDRV
Low-side driver fall time
(4)
C
LOAD
= 4.7 nF 47
I
LDRVSRPK
Low-side driver peak source current
(4)
800
mA
I
LDRVSNMIL
Low-side driver source current at 2.5 V
(4)
V
LDRV
= 2.5 V 700
I
LSDVSNPK
Low-side driver peak sink current
(4)
1.3
A
Low-side driver sink current at 2.5 V
(4)
V
LDRV
= 2.5 V 1.2
R
LDRVUP
Low-side driver pullup resistance I
LDRV
= 300 mA 2.0 4.0
Ω
R
LDRVDN
Low-side driver pulldown resistance I
LDRV
= 300 mA 0.8 1.5
I
SWLEAK
Leakage current from SW pin -1 1 µA
POWERGOOD
V
LPGD
Powergood low voltage I
PGD
= 2 mA 30 100 mV
t
PGD
Powergood delay time 15 25 35 µs
V
VDD
= OPEN, 10-kΩ pullup to external
V
LPGDNP
Powergood low voltage , no device power 1.00 1.25 V
5-V supply
V
OV
Power good overvoltage threshold, V
FB
765
mV
V
UV
Power good undervoltage threshold, V
FB
615
(3) Margining delay time is the time delay from an assertion of a margining command until the output voltage begins to transition to the
margined voltage.
(4) Ensured by design. Not production tested.
4