Datasheet

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ELECTRICAL CHARACTERISTICS
TPS40100
SLUS601MAY 2005
-40°C T
A
=T
J
85°C, V
VDD
=12V,R
RT
= 182 k,R
GM
= 232 k,R
ILIM
= 121 k (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
V
VDD
Operating range 4.5 18.0 V
OPERATING CURRENT
I
DD
Quiescent current V
FB
> 0.8 V, 0% duty cycle 1.3 1.8 2.5 mA
I
SD
Shutdown current V
UVLO
< 1 V 500 µA
5VPB
7VV
VDD
18 V, 0 mA I
LOAD
30 mA 4.7 5.0 5.3
Internal regulator V
4.5 V V
VDD
< 7 V, 0 mA I
LOAD
30 mA 4.3 5.0 5.3
OSCILLATOR/RAMP GENERATOR
f
SW
Programmable oscillator frequency 100 600
kHz
4.5 V V
VDD
<18V,
Oscillator frequency accuracy 250 275 300
-40°C T
A
=T
J
125°C
V
RAMP
Ramp amplitude
(1)
0.5 V
P-P
t
OFF
Fixed off-time 100 150 ns
D
MIN
Minimum duty cycle 0%
t
MIN
Minimum controllable pulse width
(1)
C
LOAD
= 4.7 nF, -40°C T
A
=T
J
125°C 175 ns
V
VLY
Valley voltage
(1)
1.0 1.6 2.0 V
FREQUENCY SYNCHRONIZATION
V
IH
High-level input voltage 2
V
V
IL
Low-level input voltage 0.8
I
SYNC
Input current, SYNC V
SYNC
= 2.5 V 4.0 5.5 10.0 µA
t
SYNC
Mimimum pulse width, SYNC 50
ns
t
SYNC_SH
Minimum set-up/hold time, SYNC
(2)
100
SOFT-START AND FAULT IDLE
I
SS
Soft-start source (charge) current 13 20 25
µA
I
SS_SINK
Soft-start sink (discharge) current 3.4 5.0 6.6
V
SSC
Soft-start completed voltage 3.25 3.40 3.75
V
V
SSD
Soft-start discharged voltage 0.15 0.20 0.25
Retry interval time to SS time ratio
(1)
16
V
SSOS
Offset from SS to error amplifier 300 500 800 mV
ERROR AMPLIFIER
GBWP Gain bandwidth product
(1)
3.5 5.0 MHz
AVOL Open loop 60 80 dB
I
BIAS
Input bias current, FB 50 200 nA
I
OH
High-level output current 23
mA
I
OL
Low-level output current 23
Slew rate
(1)
2.1 V/µs
FEEDBACK REFERENCE
T
A
=25°C 686 690 694
V
FB
Feedback voltage reference mV
-40°C < T
A
=T
J
125°C 683 697
(1) Ensured by design. Not production tested.
(2) To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.
3