Datasheet

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R
5
C
4
+
R
4
2 p R
1
f
cTRK
(s)
(44)
t − Time − 1 ms/div
(200 mV/div)
t
TRK
+*R
6
C
5
ln
ǒ
1 *
V
OUT
V
IN
Ǔ
(s)
(45)
TPS40100
SLUS601–MAY 2005
APPLICATION INFORMATION (continued)
Knowing the gain of the voltage loop looking into R
4
and the desired tracking loop crossover frequency, R
5
and
C
4
can be found:
where
• f
CTRK
is the desired tracking loop crossover frequency
The actual values of R
5
and C
4
are a balance between impedance level and component size. Any of a range of
values is applicable. In general, R
5
should be no more than 20% of R
6
, and less t han 10 kΩ. If this is done, then
R
6
can safely be ignored for purposes of tracking loop gain calculations. For general usage, R
6
should probably
be between 100 kΩ and 500 kΩ.
If an overshoot bump is present on the output at the beginning a tracking controlled startup, the tracking loop
bandwidth is likely too high. Reducing the bandwidth helps reduce the initial overshoot. See Figure 11 and
Figure 12.
Figure 11. Excessive Tracking Loop Bandwidth Figure 12. Limited Tracking Loop Bandwidth
The tracking ramp time is the time required for C
5
to charge to the same voltage as the output voltage of the
converter.
where
• V
OUT
is the output voltage of the converter
• V
IN
is the voltage applied to the top of R
6
• t
TRK
is the desired tracking ramp time
With these equations, it is possible to design the tracking loop so that the impedance level of the loop and the
component size are balanced for the particular application. Note that higher impedances make the loop more
susceptible to noise issues while lower impedances require increased capacitor size.
Figure 13 shows the spice model for the voltage loop expanded for use with the tracking loop.
21