Datasheet

P
QSW
+ P
CON
) P
SW
) P
GATE
(26)
P
CON
+ R
DS(on)
I
QSW(RMS)
2
+ R
DS(on)
V
OUT
V
IN
ƪ
I
out
2
)
I
RIPPLE
2
12
ƫ
(27)
P
SW
+ V
IN
f
S
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
ǒ
I
OUT
)
I
RIPPLE
2
Ǔ
ǒ
Q
gs1
) Q
gd
Ǔ
I
g
)
Q
OSS(SW)
) Q
OSS(SR)
12
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
(28)
P
GATE
+ Q
g(TOT)
V
g
f
SW
(29)
TPS40077
www.ti.com ..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
this is 11 V.
Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select
the key performance parameters. Efficiency is the performance characteristic which drives the other selection
criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in
the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.
The following equations can be used to calculate the power loss, P
QSW
, in the switching MOSFET.
where
P
CON
= conduction losses
P
SW
= switching losses
P
GATE
= gate-drive losses
Q
gd
= drain-source charge or Miller charge
Q
gs1
= gate-source post-threshold charge
I
g
= gate-drive current
Q
OSS(SW)
= switching MOSFET output charge
Q
OSS(SR)
= synchronous MOSFET output charge
Q
g(TOT)
= total gate charge from zero volts to the gate voltage
V
g
= gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28
yield preliminary values for R
DS(on)
and (Q
gs1
+ Q
gd
). Note output losses due to Q
OSS
and gate losses have been
ignored here. Once a MOSFET is selected, these parameters can be added.
The switching MOSFET for this design should have an R
DS(on)
of less than 8 m Ω . The sum of Q
gd
and Q
gs
should
be approximately 4 nC.
It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be
necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final
selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable
results. This device has an R
DS(on)
of 8 m Ω and a (Q
gs1
+ Q
gd
) of 5 nC. The estimated conduction losses are
0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W
for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output
losses of 20 mW.
Rectifier MOSFET, QSR
Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due to
the body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, so
effectively with zero switching losses. However, there are some losses in the body diode. These are minimized
by reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET turnon
and vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which helps
reduce these delays to around 10 ns.
The equations used to calculate the losses in the rectifier MOSFET are:
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s) :TPS40077