Datasheet

C u
V
IN
* 8 V
R SR
(1)
R t
0.2 V
f
SW
Q
g(TOT)
) I
DD
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
R
T
+
ǒ
1
f
SW
(kHz) 17.82 10
*6
* 23
Ǔ
kW
(3)
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO
R
KFF
+ 0.131 R
T
V
UVLO(on)
* 1.61 10
*3
V
UVLO(on)
2
) 1.886 V
UVLO
* 1.363 * 0.02 R
T
* 4.87 10
*5
R
2
T
TPS40077
www.ti.com ..................................................................................................................................................... SLUS714D – JANUARY 2007 – REVISED APRIL 2009
where
• V
VIN
is the final value of the input voltage ramp
• f
SW
is the switching frequency
• Q
g(TOT)
is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
• I
DD
is the TPS40077 input current (3.5 mA maximum)
• SR is the maximum allowed slew rate [12 × 10
4
] (V/s)
The TPS40077 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as
the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching
frequency of the clock oscillator. The clock frequency is related to R
T
by:
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations,
because the PWM is not required to wait for loop delays before changing the duty cycle. (See Figure 23 ).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to
start. The PWM ramp time is programmed via a single resistor (R
KFF
) connected from KFF VDD. R
KFF
, V
START
,
and R
T
are related by (approximately):
(4)
where
• R
T
and R
KFF
are in k Ω
• V
UVLO(on)
is in V
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up
to ± 15% from this number. Figure 16 through Figure 18 show the typical relationship of V
UVLO(on)
, V
UVLO(off)
and
R
KFF
at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For
example, if the startup voltage is programmed to be 10 V, the controller starts when V
DD
reaches 10 V and shuts
down when V
DD
falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice
the startup voltage. Below this point, the maximum duty cycle is as specified in the Electrical Characteristics
table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is
approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal
to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and
below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V.
Figure 23 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages.
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