Datasheet

APPLICATION INFORMATION
MINIMUM PULSE DURATION
SLEW RATE LIMIT ON VDD
15
9
16
13
12
10
ILIM
HDRV
SW
LDRV
VDD
PGND
TPS40077
C
R
VIN
S0203-01
+
_
TPS40077
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for
increased efficiency and improved converter output-power capability. Voltage feed-forward is employed to ease
loop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking current
from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integrated
power-good indicator is available for logic (open-drain) output of the condition of the output of the converter.
The TPS40077 devices have limitations on the minimum pulse duration that can be used to design a converter.
Reliable operation is assured for nominal pulse durations of 150 ns and above. This places some restrictions on
the conversion ratio that can be achieved at a given switching frequency. Figure 14 shows minimum output
voltage for a given input voltage and frequency.
The regulator that supplies power for the drivers on the TPS40077 requires a limited rising slew rate on VDD for
proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can overshoot and
damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than
0.12 V/ µ s as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the
device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from
the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in
normal operation. This places some constraints on the R-C values that can be used. Figure 22 is a schematic
fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R
and C that limit the slew rate in the worst-case condition.
Figure 22. Limiting the Slew Rate
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