Datasheet

www.ti.com
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
T
A
= – 40 ° C to 85 ° C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω , I
KFF
= 300 µA, f
SW
= 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
OFF
Off time during a fault (SS cycle times) 7 cycles
V
SW
Switching level to end precondition
(1)
(V
VDD
- V
SW
) 2 V
t
PC
Precondition time
(2)
100 ns
V
ILIM(pre)
Current limit precondition voltage threshold
(2)
6.8 V
OUTPUT DRIVERS
t
HFALL
High-side driver fall time
(2)
36
C
HDRV
= 2200 pF, (HDRV - SW) ns
t
HRISE
High-side driver rise time
(2)
48
t
HFALL
High-side driver fall time
(2)
72
C
HDRV
= 2200 pF, (HDRV - SW)
ns
V
VDD
= 4.5 V
t
HRISE
High-side driver rise time
(2)
96
t
LFALL
Low-side driver fall time
(2)
24
C
LDRV
= 2200 pF ns
t
LRISE
Low-side driver rise time
(2)
48
t
LFALL
Low-side driver fall time
(2)
48
C
LDRV
= 2200 pF, V
DD
= 4.5 V ns
t
LRISE
Low-side driver rise time
(2)
96
I
HDRV
= -0.01 A, (V
BOOST
- V
HDRV
) 0.7 1.0
V
OH
High-level output voltage, HDRV V
I
HDRV
= -0.1 A, (V
BOOST
- V
HDRV
) 0.95 1.35
(V
HDRV
- V
SW
), I
HDRV
= 0.01A 0.06 0.10
V
OL
Low-level output voltage, HDRV V
(V
HDRV
- V
SW
), I
HDRV
= 0.1 A 0.65 1.00
(V
DBP
- V
LDRV
), I
LDRV
= -0.01A 0.65 1.00
V
OH
High-level output voltage, LDRV V
(V
DBP
- V
LDRV
), I
LDRV
= -0.1 A 0.875 1.300
I
LDRV
= 0.01 A 0.03 0.05
V
OL
Low-level output voltage, LDRV V
I
LDRV
= 0.1 A 0.3 0.5
BOOST REGULATOR
V
BOOST
Output voltage V
VDD
= 12 V 15.2 17.0 V
UVLO
V
UVLO
Programmable UVLO threshold voltage R
KFF
= 90.9 k Ω , turn-on, V
VDD
rising 6.2 7.2 8.2
Programmable UVLO hysteresis R
KFF
= 90.9 k Ω 1.10 1.55 2.00 V
Fixed UVLO threshold voltage Turn-on, V
VDD
rising 4.15 4.30 4.45
Fixed UVLO hysteresis 275 365 mV
POWER GOOD
V
PGD
Powergood voltage I
PGD
= 1 mA 370 550
V
FBH
High-level output voltage, FB 770 mV
V
FBL
Low-level output voltage, FB 630
SENSE AMPLIFIER
V
SA+
= V
SA-
= 1.25 V, Offset referenced to
V
IO
Input offset voltage -9 9 mV
SA+ and SA-
A
DIFF
Differential gain V
SA+
- V
SA-
= 4.5 V 0.995 1.000 1.005
V
ICM
Input common mode range
(3)
0 6 V
R
G
Internal resistance for setting gain 14 20 26 k Ω
I
OH
Output source current 2 10 15
mA
I
OL
Output sink current 15 25 35
GBWP Gain bandwidth
(4)
2 MHz
THERMAL SHUTDOWN
(2) Ensured by design. Not production tested.
(3) 3 V at internal amplifier terminals, 6 V at SA+ and SA- pins.
(4) Ensured by design. Not production tested.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :TPS40075