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DESIGN EXAMPLE
1. SPECIFICATIONS
2. SCHEMATIC
R
P1
R
Z1
R
PGD
C
O
C
Z2
R
SET2
R
KFF
1
2
3
4
19
18
17
16
SYNC
PGD
LVBP
RT
SA−
SAO
GND
SS
TPS40075
15
14
13
12
KFF
ILIM
VDD
HDRV
5
6
7
8
FB
COMP
PGND
LDRV
9 DBP
20
SA+
10
SW
11
BOOST
UDG−04125
SYNC
−SENSE
QSR
MLCCELCO
QSW
+SENSE
ELCO
0V
R
LIM
C
LIM
L
C
O
V
O
C
VDD
C
VLVBP
C
PZ1
C
IN
V
IN
R
PZ2
C
P2
R
SET1
C
SS
C
DBP
D
BOOST
C
BOOST
R
T
1.5 Ω
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENT
V
IN
Input voltage 10.8 12.0 13.2
V
O
Output voltage I
OUT
= 10 A 1.5 5 V
Regulation 1.47 1.53
V
RIPPLE
Output ripple voltage I
O(max)
= 15 A 30
V
OVER
Output overshoot I
STEP
= 8 A 50 mV
V
UNDER
Output undershoot I
STEP
= 8 A 50
I
LOAD
Output current 0 15
A
I
SCP
Short circuit current trip point 16 30
η Efficiency V
IN
= 12 V, I
LOAD
= 15 A 85%
f
SW
Switching frequency 400 kHz
Figure 29. TPS40075 Reference Design Schematic
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