Datasheet

www.ti.com
VDG−03174
t
BLANKING
7 Current Limit Trips
(HDRV Cycle Terminated by Current Limit Trip)
7
Soft-Start
Cycles
HDRV
Clock
V
ILIM
V
VIN
−V
SW
SS
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
The comparator that looks at ILIM and SW to determine if a short circuit condition exists has a clamp on its SW
input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as
2 V at – 40 ° C) below VDD. While ILIM is more than 1.4 V below VDD short circuit sensing is effectively disabled,
giving a programmable absolute blanking time. As a general rule, it is best to make the time constant of the R-C
at the ILIM pin 20% or less of the nominal pulse width of the converter (See Equation 11 )
The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an
overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches
seven (7) a fault condition is declared by the controller. When this happens, the output drivers turn both
MOSFETs off. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the
PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is
decremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removed
the output starts up normally. If the output fault is still present the counter counts seven overcurrent pulses and
re-enters the second tier fault mode. Refer to Figure 28 for typical fault protection waveforms.
Figure 28. Typical Fault Protection Waveforms
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :TPS40075