Datasheet

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APPLICATION INFORMATION

MINIMUM PULSE WIDTH

SLEW RATE LIMIT ON VDD

ILIM

HDRV

LDRV

VDD

PGND

TPS40075

VIN

UDG−05058

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

The TPS40075 allows the user to construct synchronous voltage mode buck converters with inputs ranging from

4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for

increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease

loop compensation for wide input range designs and provide better line transient response.

An on-board unity gain differential amplifier is provided for remote sensing in applications that require the tightest

load regulation. The TPS40075 incorporates circuitry to allow startup into a pre-existing output voltage without

sinking current from the source of the pre-existing output voltage. This avoids damaging sensitive loads at

startup. The controller can be synchronized to an external clock source or can free run at a user programmable

frequency. An integrated power good indicator is available for logic (open drain) output of the condition of the

output of the converter.

The TPS40075 has limitations on the minimum pulse width that can be used to design a converter. Reliable

operation is guaranteed for nominal pulse widths of 150 ns and above. This places some restrictions on the

conversion ratio that can be achieved at a given switching frequency. See Figure 16 .

The regulator that supplies power for the drivers on the TPS40075 requires a limited rising slew rate on VDD for

proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot and

damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than

0.12 V/ μ s as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the

device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from

the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in

normal operation. This places some constraints on the R-C values that can be used. Figure 25 is a schematic

fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R

and C that limits the slew rate in the worst case condition.

Figure 25. Limiting the Slew Rate

Product Folder Link(s) :TPS40075