Datasheet

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9
12
8
13
17
16
15
VDD
LVBP
RT
KFF
DBP
HDRV
LDRV
18
3
5
4
PGD
GND
FB
SS
6COMP
Reference
Regulator
Predictive
Gate Drive
Control
Logic
UVLO
Controller
Oscillator
14 ILIM
Pulse
Control
SW
CLK
10 SW
Overcurrent
Comparator
and Control
CLK
ILIM OC
7 PGND
11 BOOST
VDD
UVLO
Ramp
Generator
Power
Good
Logic
770 mV
FB
630 mV
SS Active
PWM
OC
CLK
UVLO
FAULT
IZERO
DBP
+
+
700 mV
RAMP
Soft Start
and
Fault Control
OC
CLK
SW
PGND
LVBP
2SAO
20 SA+
1 SA−
R
R
R
+
R
UDG−04076
19SYNC
TPS40075
TPS40075
SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007
SIMPLIFIED BLOCK DIAGRAM
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