Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers VQFN 20

FEATURES

APPLICATIONS

CONTENTS

DESCRIPTION

SYNC

PGD

LVBP

SA−

SAO

GND

TPS40075

KFF

ILIM

VDD

HDRV

COMP

PGND

LDRV

9 DBP

SA+

BOOST

SYNC IN

PowerGood OUT

UDG−04075

OUT

−

OUT

−

(at Load)

OUT

(at Load)

TPS40075

SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007

www.ti.com

MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER

WITH VOLTAGE FEED-FORWARD

The TPS40075 drives external N-channel MOSFETs

using second generation Predictive Gate Drive to

• Operation Over 4.5-V to 28-V Input Range

minimize conduction in the body diode of the low side

• Fixed-Frequency Voltage-Mode Controller

FET and maximize efficiency. Pre-biased outputs are

supported by not allowing the low side FET to turn on

• Integrated Unity Gain Amplifier for Remote

until the voltage commanded by the closed loop soft

Output Sensing

start is greater than the pre-bias voltage. Voltage

• Predictive Gate Drive™ Generation II for

feed forward provides good response to input

Improved Efficiency

transients and provides a constant PWM gain over a

• <1% Internal 700-mV Reference

wide input voltage operating range to ease

compensation requirements. Programmable short

• Input Voltage Feed Forward Control

circuit protection provides fault current limiting and

• Prebiased Output Compatible

hiccup recovery to minimize power dissipation with a

• Internal Gate Drive Outputs for High-Side and

shorted output. The 20-pin QFN package gives good

Synchronous N-Channel MOSFETs

thermal performance and a compact footprint.

• Switching Frequency Programmable to 1 MHz

SIMPLIFIED APPLICATION DIAGRAM

• 20-Pin QFN Package

• Thermal Shutdown Protection

• Software Design Tool and EVM Available

• Power Modules

• Networking/Telecom

• Industrial

• Servers

Device Ratings 2

Electrical Characteristics 4

Terminal Information 12

Application Information 15

Design Example 26

Additional References 40

The TPS40075 is a mid voltage, wide input (4.5-V to

28-V), synchronous, step-down controller, offering

design flexibility for a variety of user programmable

functions, including; soft start, UVLO, operating

frequency, voltage feed-forward and high-side FET

sensed short circuit protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Predictive Gate Drive is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

PAGE 1
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD FEATURES 1 • Operation Over 4.
PAGE 2
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ORDERING INFORMATION (1) (2) TA PACKAGE 40°C to 85°C Plastic QFN (RHL) PART NUMBER TPS40075RHLT (1) TPS40075RHLR (2) The TPS40075 is available taped and reeled only. Add an T suffix (i.e. TPS40075RHLT) to the orderable part number for quantities of 250 units per small reel. . Add an R suffix (i.e. TPS40075RHLR) to the orderable part number for quantities of 3,000 units per large reel.
PAGE 3
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 RECOMMENDED OPERATING CONDITIIONS MIN NOM MAX UNIT VDD Input voltage 4.5 28 V TA Operating free-air temperature -40 85 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER MIN TYP Human body model 1500 CDM 1500 MAX UNIT V PACKAGE DISSIPATION RATINGS (1) (1) AIRFLOW (LFM) THERMAL IMPEDANCE JUNCTION-TO-AMBIENT (°C/W) TA = 25°C POWER RATING (W) TA = 85°C POWER RATING (W) Natural Convection 42 2.38 0.
PAGE 4
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range, VIN 4.5 28 V 2.5 3.5 mA 4.2 4.5 V OPERATING CURRENT IDD Quiescent current Output drivers not switching Output voltage TA = TJ = 25°C LVBP VLVBP 3.
PAGE 5
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.
PAGE 6
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Shutdown temperature threshold (4) TYP MAX 165 Hysteresis (4) UNIT °C 15 TYPICAL CHARACTERISTICS LVBP VOLTAGE vs JUNCTION TEMPERATURE DBP VOLTAGE vs JUNCTION TEMPERATURE 8.15 4.30 8.
PAGE 7
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) DBP VOLTAGE vs JUNCTION TEMPERATURE BOOTSTRAP DIODE VOLTAGE vs JUNCTION TEMPERATURE 4.50 2.0 VDD = 4.5 V ILOAD = 25 mA 1.9 VDROP − Bootstrap Diode Voltage Drop − V 4.49 VDBP − DBP Voltage − V 4.48 4.47 4.46 4.45 4.44 4.43 4.42 4.41 4.40 −50 −25 0 25 50 100 75 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.
PAGE 8
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) FEEDBACK REGULATION VOLTAGE vs JUNCTION TEMPERATURE SENSE AMPLIFIER OUTPUT CURRENT vs JUNCTION TEMPERATURE 704 30 VFB − Feedback Voltage − V 703 ISENSE − Sense Amplifier Output Current − mA VDD 28 V 4.
PAGE 9
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 93 VUVLO − Undervoltage Lockout Threshold − V 4.35 DMAX − Maximum Duty Cycle − % 92 91 fSW = 100 kHZ 90 89 88 fSW = 500 kHZ 87 86 85 fSW = 1 MHZ 84 83 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C VUVLO(on) 4.20 4.15 4.10 4.05 4.00 VUVLO(off) 3.
PAGE 10
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) ERROR AMPLIFIER INPUT BIAS CURRENT vs JUNCTION TEMPERATURE MINIMUM OUTPUT VOLTAGE vs FREQUENCY 5.0 −10 VIN = 28 V 4.5 −20 VOUT − Output Voltage − V IBIAS − Error Amplifier Input Bias Current − nA 0 −30 −40 −50 −60 VIN = 8 V 2.5 50 75 100 VIN = 5 V 2.0 1.0 25 VIN = 10 V 3.0 −80 0 VIN = 15 V VIN = 12 V 3.5 1.5 −25 VIN = 18 V 4.0 −70 −90 −50 VIN = 24 V 0.
PAGE 11
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE UVLO THRESHOLD VOLTAGE vs FEEDFORWARD IMPEDANCE 20 20 fSW = 500 kHz UVLOVON 18 VUVLO − Programmable UVLO Threshold − V VUVLO − Programmable UVLO Threshold − V fSW = 300 kHz 16 14 12 UVLOVOFF 10 8 6 4 2 100 16 14 12 UVLOVOFF 10 8 6 4 2 150 200 250 300 350 400 60 450 90 RKFF − Feedforward Impedance − kΩ Figure 19.
PAGE 12
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) INPUT VOLTAGE vs DBP VOLTAGE INPUT VOLTAGE vs LOW VOLTAGE BYPASS VOLTAGE 4.50 VDBP − Low Voltage Bypass Voltage − V VDBP − Driver Bypass Voltage − V 10 9 8 7 6 5 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 4 0 5 10 15 VDD − Input Voltage − V Figure 23. 20 5 25 10 15 20 25 30 VDD − Input Voltage − V Figure 24.
PAGE 13
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Table 1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 11 I The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is the available drive voltage for the high-side FET.
PAGE 14
TPS40075 www.ti.
PAGE 15
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION The TPS40075 allows the user to construct synchronous voltage mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease loop compensation for wide input range designs and provide better line transient response.
PAGE 16
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Rt f SW 0.2 V Q g(TOT) ) I IDD (1) V *8V C u VIN R SR (2) where • • • • • VVIN is the final value of the input voltage ramp fSW is the switching frequency Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet) IIDD is the TPS40075 input current (3.
PAGE 17
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Figure 26 shows the effect of changing input voltage on the duty cycle, and how that change takes place. The pulse width modulator (PWM) ramp input is generated using a current that is proportional to the current into the KFF pin. The TPS40075 holds this pin at a constant 400 mV, so connecting a resistor from KFF to the input power supply causes a current to flow into the KFF pin that is proportional to the input voltage.
PAGE 18
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 PROGRAMMING SHORT CIRCUIT PROTECTION The TPS40075 uses a two-tier approach to short circuit protection. The first tier is a pulse-by-pulse protection scheme. Short circuit protection is implemented by sensing the voltage drop across the high-side MOSFET while it is turned on. The MOSFET drain to source voltage is compared to the voltage dropped across a resistor (RILIM) connected from VDD to the ILIM pin.
PAGE 19
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The comparator that looks at ILIM and SW to determine if a short circuit condition exists has a clamp on its SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as 2 V at – 40°C) below VDD. While ILIM is more than 1.4 V below VDD short circuit sensing is effectively disabled, giving a programmable absolute blanking time.
PAGE 20
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The minimum short circuit limit threshold (ISCP) depends on tSTART, COUT, VOUT, and the load current at turn-on (ILOAD).
PAGE 21
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 DIFFERENTIAL SENSE AMPLIFIER The TPS40075 has an on board differential amplifier intended for use as a remote sensing amplifier for the output voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops that occur between the converter and the actual point of load. The amplifier is powered from the DBP pin and can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V.
PAGE 22
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Automatic startup sequencing can be accomplished by connecting the PGD pin of a master supply based on the TPS40075 to the SS pin of a slave supply. The master comes up first and release the salve SS pin to allow the slave to come up.
PAGE 23
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 GROUNDING AND BOARD LAYOUT The TPS40075 provides separate signal ground (GND) and power ground (PGND) pins. Care should be given to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane.
PAGE 24
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 DESIGN EXAMPLE 1. SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.8 12.0 13.2 INPUT CURRENT VIN Input voltage VO Output voltage IOUT = 10 A 1.5 Regulation 1.47 5 V 1.
PAGE 25
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3. COMPONENT SELECTION 3. 1 Power Train Components Designers familiar with the buck converter can skip to section 3.2 Component Selection for TPS40075. 3.1.1 Output Inductor, LO The output inductor is one of the most important components to select. It stores the energy necessary to keep the output regulated when the switch MOSFET is turned off. The value of the output inductor dictates the peak and RMS currents in the converter.
PAGE 26
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3.1.3. Input Capacitor, CIN, ELCO and MLCC The input capacitor is selected to handle the ripple current of the buck stage. Also a relative large capacitance is used to keep the ripple voltage on the supply line low. This is especially important where the supply line is high impedance. It is recommended that the supply line be kept low impedance. The input capacitor ripple current can be calculated using Equation 23.
PAGE 27
TPS40075 www.ti.
PAGE 28
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 The calculations for the losses in the rectifier MOSFET are show in Equation 29 through Equation 32.
PAGE 29
TPS40075 www.ti.com R KFF + SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ǒVUVLO(on) * 0.5Ǔ ǒ 0.018 ) ǒ ǓǓ 5 RT (34) This equation gives a RKFF value of 136 kΩ. The closest lower standard value should be selected. For this design and using E24 resistor range 133 kΩ was chosen. This yields a typical start voltage of 8.52 V. 3.2.3 Soft Start Capacitor It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible damage to the load.
PAGE 30
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 3.2.5 Voltage Decoupling Capacitors, CDBP, CLVBP and CVDD Several pins on the TPS40075 have DC voltages. It is recommended to add small decoupling capacitors to these pins. Below is a list of the recommended values. • CDBP = 1.0 μF • CLVBP = 0.1 μF • CVDD = 4.7 μF 3.2.6 Boost Voltage, CBOOST and DBOOST (optional) A capacitor charge pump or boost circuit is required to drive an N-channel MOSFET in the switch location of a buck converter .
PAGE 31
TPS40075 www.ti.com f LC_Pole + SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 ǸL 2p f ESR_Zero + 2p CO 1 ESR + 3559 Hz (47) CO + 8377 Hz (48) The resulting bode plot is shown in Figure 30. 30 Double Pole 20 10 ESR Zero Gain − dB 0 −10 ESR = 0.0095 Ω Slope = −20 dB / decade −20 −40 ESR = 0 Ω Slope = −40 dB / decade −50 −60 100 1k 10 k 100 k 1M Frequency − Hz Figure 30.
PAGE 32
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 A typical bode plot to this type of compensation network is shown in Figure 32. 40 Gain − dB 30 High Frequency Gain 20 10 0 −10 −20 100 1k fZ1 10 k fP1 fZ2 Frequency − Hz 100 k 1M fP2 Figure 32. Type III Compensation Bode Plot The high frequency gain and the break (pole and zero) frequencies are calculated using the following equations.
PAGE 33
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 Desired frequency response and resultant overall system response can be seen in Figure 33. 40 Overall System Response ESR = 0 Ω 30 20 GBWP Overall System Response ESR = 0.0095 Ω Gain − dB 10 0 −10 −20 −30 −40 −50 Compensation Response PWM and LC Response ESR = 0 Ω PWM and LC Response ESR = 0.0095 Ω fCO2 −60 100 1k fCO1 10 k 100 k 1M Frequency − Hz Figure 33.
PAGE 34
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 GAIN vs FREQUENCY PHASE vs FREQUENCY 200 60 180 40 System Gain ESR = 0.95 mΩ 140 Phase − ° 20 Gain − dB System Phase ESR = 0 Ω 160 0 120 100 80 −20 60 40 −40 System Gain ESR = 0 Ω −60 100 1k 10 k Frequency − Hz 20 100 k 1M 0 100 System Phase ESR = 0.95 mΩ 1k Figure 34. 10 k 100 k Frequency − Hz 1M Figure 35. ALTERNATE APPLICATIONS Some alternative applicaiton diagrams are shown in Figure 36 through Figure 38.
PAGE 35
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 20 External Logic Supply SA− SA+ TPS40075 402 Ω 10 nF 10 kΩ 2 SAO SYNC 19 3 GND PGD 18 4 SS 5 FB 6 COMP 14 kΩ Power Good 1 µF LVBP 17 2 nF 2 nF 10 kΩ VDD 12 V 118 kΩ RT 16 10 kΩ 118 kΩ KFF 15 75 pF 1.27 kΩ 120 µF 120 µF ILIM 14 7 PGND 8 LDRV 22 pF VDD 13 1 µF Si7390DP 9 DBP 22 µF HDRV 12 SW BOOST 10 11 22 µF 100 nF 1.3 µH 1.
PAGE 36
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 1 20 SA− SA+ TPS40075 294 Ω 2 SAO SYNC 19 3 GND PGD 18 1 µF 10 nF 10 kΩ LVBP 17 330 kΩ 4 SS 5 FB VDD 5 V to 12 V 165 kΩ 3.9 nF 3.3 nF From 3.3 V Logic Clock Source RT 16 88.7 kΩ 11.3 kΩ 6 KFF 15 COMP 120 µF 120 µF 1.74 kΩ 100 pF ILIM 14 2.67 kΩ 7 PGND 8 LDRV 39 pF VDD 13 1 µF Si7344DP 9 DBP 22 µF HDRV 12 SW BOOST 10 11 22 µF 100 nF 2.2 µH BAT54 1.5 Ω 100 nF 3.
PAGE 37
14 kΩ 10 kΩ Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s) :TPS40075 1 µF 75 pF 10 kΩ 10 nF Si7868DP 2 nF 2 nF 402 Ω HDRV 12 VDD 13 ILIM 14 KFF 15 RT 16 LVBP 17 PGD 18 SYNC 19 10 100 n 1.5 Ω 11 SW BOOST 9 DBP 8 LDRV 7 PGND 6 COMP FB 4 SS 3 GND 5 20 SA− SA+ TPS40075 1 2 SAO SYNC Clock Input 300 kHz 10 kΩ 100 nF Si7390DP 22 µF 120 µF 100 µF × 3 22 µF 120 µF 13 µH VDD, 12 V 22 pF 1.27 kΩ 205 kΩ 215 kΩ 1 µF SN74LVC1G04 1.
PAGE 38
TPS40075 www.ti.com SLUS676A – MAY 2006 – REVISED SEPTEMBER 2007 ADDITIONAL REFERENCES The following parts are similar to the TPS40075 and may be of interest: 1. TPS40071 Mid Range Input (4.5 V to 28 V) up to 1-MHz Frequency Synchronous Buck Controller 2. TPS40100 Wide Input Range Synchronous Buck Controller for Sequencing 3. TPS40057 Wide Input (8 V to 40 V) up to 1MHz Frequency Synchronous Buck Controller, source/sink with prebias 4.
PAGE 39
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40075RHLR VQFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS40075RHLT VQFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.
PAGE 40
PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40075RHLR VQFN RHL 20 3000 367.0 367.0 35.0 TPS40075RHLT VQFN RHL 20 250 210.0 185.0 35.
PAGE 41
PAGE 42
PAGE 43
PAGE 44
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.