Datasheet

C
BP10V
+
Q
gSR
DV
+
57 nC
0.5
+ 114 nF
C
BPN10
+
Q
g
DV
+
30 nC
0.5
+ 60 nF
R
BIAS
+
0.7 V R1
V
O
* 0.7 V
+
0.7 V 100kW
3.3 V * 0.7 V
+ 26.9 kW, choose 26.7 kW
Z1
1 1
f C1 4301 pF, choose 3900 pF
2 R2 C1 2 10 k 3.7 kHz
= \ = =
p ´ ´ p ´ W ´
P1
1 1
f R2 9.82 k , choose 10 k
2 R2 C2 2 220 pF 73.7 kHz
= \ = = W W
p ´ ´ p ´ ´
C
1 1
f C2 196 pF, choose 220 pF
2 R1 C2 G 2 100 k 0.81 10 kHz
= \ = =
p ´ ´ ´ p ´ W ´ ´
P2
1 1
f R3 4.59 k , choose 4.64 k
2 R3 C3 2 470 pF 73.7 kHz
= \ = = W W
p ´ ´ p ´ ´
f
Z2
+
1
2p R1 C3
N C3 +
1
2p 100 kW 3.7 kHz
+ 430 pF, choose 470 pF
MOD(f )
1 1
G 0.81
A 1.23
= = =
2
2
LC
MOD(f ) MOD
C
f
3.7 kHz
A A 9 1.23
f 10 kHz
æ ö
æ ö
= ´ = ´ =
ç ÷
ç ÷
è ø
è ø
TPS40060
TPS40061
www.ti.com SLUS543F –DECEMBER 2002–REVISED JUNE 2013
The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 27.
(70)
And also from Equation 27.
(71)
Choose R1 = 100 kΩ
The poles and zeros for a Type III network are described in Equation 25 and Equation 26.
(72)
(73)
(74)
(75)
(76)
Calculate the value of R
BIAS
from Equation 23 with R1 = 100 kΩ.
(77)
CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin
from Equation 8 is shown in Equation 78.
(78)
and the BP10V capacitance from Equation 9 is shown in Equation 79.
(79)
For this application, a 0.1-µF capacitor was used for the BPN10V and a 1.0-µF was used for the BP10V bypass
capacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter
specified in the design example.
GATE DRIVE CONFIGURATION
Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high V
DS
voltage and low
gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The
resistor can be used to shape the low-to-high transition of the Switch node and reduce the tendency of dv/dt-
induced turn on.
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