Datasheet

TPS40060
TPS40061
SLUS543F –DECEMBER 2002–REVISED JUNE 2013 www.ti.com
LAYOUT CONSIDERATIONS
THE PowerPAD™ PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad
are shown in Figure 13.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally
Enhanced Package (see REFERENCES section) for more information on the PowerPAD package.
Figure 13. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θ
JA
)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The θ
JA
specified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper
on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer
to the selected MOSFET's data sheet for more information regarding proper mounting.
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit
grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible.
The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor
(BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, R
T
, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
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