Datasheet

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SLVS612 − APRIL 2006
25
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DESIGN EXAMPLE
The poles and zeros for a type III network are described in equations (20) and (21).
f
Z2
+
1
2p R1 C3
N C3 +
1
2p 100 kW 3.05 kHz
+ 522 pF, choose 560 pF
f
P2
+
1
2p R3 C3
N R3 +
1
2p 560 pF 28.2 kHz
+ 10.08 kW, choose 10 kW
f
C
+
1
2p R1 C2 G
N C2 +
1
2p 100 kW 7.14 20 kHz
+ 11.1 pF, choose 10 pF
f
P1
+
1
2p R2 C2
N R2 +
1
2p 10 pF 28.2 kHz
+ 564 kW, choose 562 kW
f
Z1
+
1
2p R2 C1
N C1 +
1
2p 562 kW 3.05 kHz
+ 92.9 pF, choose 100 pF
Calculate the value of R
BIAS
from equation (17) with R1 = 100 kΩ. Since the output of 1.25-V is within the
EA_REF input specification of 0.5 V to 1.5 V, an R
BIAS
resistor is not required.
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop
on the BOOST pin from equation (24) is:
C
BOOST
+
Q
g
DV
+
18 nC
0.5 V
+ 36 nF
and the BP10V capacitance from (25) is
C
BP(10 V)
+
Q
gHS
) Q
gSR
DV
+
2 Q
g
DV
+
36 nC
0.5 V
+ 72 nF
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used
for the BP10V bypass.
Figure 10 shows component selection for the 10-V to 14.4-V to 1.25-V at 8 A dc-to-dc converter specified in the
design example.
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM−1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief: TI
Literature No. SLMA002
(67)
(68)
(69)
(70)
(71)
(72)
(73)