Datasheet

UDG-02136
HDRV
CLOCK
V
VIN
-V
SW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)
7 SOFT-START CYCLES
V
ILIM
t
BLANKING
( )
O O
ILIM LOAD
START
C V
I I A
t
æ ö
´
= +
ç ÷
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TPS40054
TPS40055
TPS40057
SLUS593H DECEMBER 2003REVISED JULY 2012
www.ti.com
PROGRAMMING CURRENT LIMIT
The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM
is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 9 for typical overcurrent
protection waveforms.
The minimum current limit setpoint (I
ILIM
) is calculated in Equation 14.
where
I
LOAD
is the load current at start-up (14)
Figure 9. Typical Current Limit Protection Waveforms
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