Datasheet

100 1 k 10 k 100 k
Switching Frequency (Hz)
Modulator Gain (dB)
ESR Zero, +1
A
MOD
= V
IN(min)
/V
RAMP
L-C Filter, –2
Resultant, –1
D= V
C
/V
S
V
S
V
C
f
C
+
f
SW
4
(Hertz)
BIAS
O
0.7 R1
R
V 0.7
´
= W
-
f
Z
+
1
2p ESR C
O
(Hertz)
f
LC
+
1
2p L C
O
Ǹ
(Hertz)
( )
( )
( )
IN min IN min
MOD
MOD dB
RAMP RAMP
V V
A or A 20 log
V V
æ ö æ ö
ç ÷ ç ÷
= = ´
ç ÷ ç ÷
è ø è ø
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012 www.ti.com
For the TPS4005x, with V
IN(min)
being the minimum input voltage required to cause the ramp excursion to reach
the maximum ramp amplitude of V
RAMP
, the modulator dc gain is shown in Equation 19.
(19)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-C
O
. The double pole
is located at the frequency calculated in Equation 20.
(20)
There is also a zero created by the output capacitance, C
O
, and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 21.
(21)
Calculate the value of R
BIAS
to set the output voltage, V
O
.
(22)
The maximum crossover frequency (0 dB loop gain) is set by Equation 23.
(23)
Typically, f
C
is selected to be close to the midpoint between the L-C
O
double pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 11 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
Figure 10. PWM Modulator Relationships Figure 11. Modulator Gain vs Switching Frequency
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