Datasheet

1
2
3
4
16
15
14
13
ILIM
VIN
BOOST
HDRV
KFF
RT
BP5
SYNC
TPS4005xPWP
5
6
7
8
12
11
10
9
SW
BP10
LDRV
PGND
SGND
SS
VFB
COMP
D
A
1N914, 1N4150
Type Signal Diode
PGND
R
A
499 kW
C
A
47 pF
R
KFF
71.5 kW
UDG-08102
( )
( )
f
A
A SW
8 3.48
C
R 7.9
-
=
´ ´
( )
( )
(
)
KFF
A
IN min
R 8 3.48
R 495 k 499 k
0.1 V 3.48
´ -
= = W = W
´ -
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012 www.ti.com
Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This
applies to applications which have high impedance on the input voltage line or which have excessive ringing on
the V
IN
line. The input voltage impedance can cause the input voltage to sag enough at start up to cause a
UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and
cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to
prevent the nuisance UVLO shutdown.
Assuming a hysteresis current of 10% I
KFF
, and the peak detector charges to 8 V and V
IN(min)
= 10 V, the value of
R
A
is calculated by Equation 3 using a R
KFF
= 71.5 kΩ.
(3)
C
A
is chosen to maintain the peak voltage between switching cycles in order to keep the capacitor charge from
drooping 0.1 V (from 8 V to 7.9 V).
(4)
The value of C
A
may calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The
diode can be a small-signal switching diode or Schottky rated for more then 20 V. Figure 6 illustrates a typical
implementation using a small switching diode.
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start up voltage.
Figure 6. Hysteresis for Programmable UVLO
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