Datasheet

TPS40055-EP
www.ti.com SGLS310D –JULY 2005–REVISED FEBRUARY 2012
R
T
is the timing resistance in kΩ.
The curve showing the R
KFF
required for a given switching frequency (f
SW
) is shown in Figure 4.
For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltage. For more information on large duty cycle operation, see the application note
(SLUA310).
SWITCHING FREQUENCY FEED-FORWARD IMPEDANCE
vs vs
TIMING RESISTANCE SWITCHING FREQUENCY
Figure 3. Figure 4.
UVLO OPERATION
The TPS40055 uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start low
until the input voltage has exceeded the user programmable undervoltage threshold.
The TPS40055 uses the feed-forward pin, KFF, as a user programmable low-line UVLO detection. This variable
low-line TPS40055 uses variable (user programmable) UVLO protection. The UVLO circuit holds the soft-start
low until the input voltage has exceeded the user programmable undervoltage threshold. UVLO threshold
compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the
TPS40055 receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a
function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function
of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the
oscillator frequency as described in Equation 3:
(3)
where:
V
IN
is the desired start-up (UVLO) input voltage
R
T
is the timing resistance in kΩ
The variable UVLO function uses a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or
fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than
the clock cycle a power-good signal is asserted and a soft-start initiated and the upper and lower MOSFETS are
turned off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 5 ).
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