Datasheet

W
97
TPS40055-EP
SGLS310D –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
8. Programming the ramp generator circuit
The PWM ramp is programmed through a resistor (R
KFF
) from the KFF pin to V
IN
. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, R
KFF
can be calculated from Equation 64.
(64)
9. Calculating the output capacitance (C
O
)
In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A
to 8-A step load. C
O
can be calculated using Equation 65.
(65)
Using Equation 66, we can calculate the ESR required to meet the output ripple requirements.
(66)
(67)
For this design example, two Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
10. Calculate the soft-start capacitor (C
SS
)
This design requires a soft-start time (t
START
) of 1 ms. C
SS
can be calculated on Equation 68
(68)
11. Calculate the current limit resistor (R
ILIM
)
The current limit set point depends on t
START
, V
O
, C
O
, and I
LOAD
at start-up as shown in Equation 69. For this
design,
(69)
For this design, set I
LIM
for 11 A
DC
minimum. From Equation 70, with I
OC
equal to the dc-output surge current
plus one-half the ripple current of 3.2 A and R
DS(on)
is increased 30% (1.3 × 0.008) to allow for MOSFET heating.
(70)
12. Calculate loop compensation values
Calculate the dc modulator gain (A
MOD
) from Equation 71
(71)
Calculate the output filter L-C
O
poles and C
O
ESR zeros from Equation 72 and Equation 73
(72)
and
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