Datasheet

TPS40055-EP
SGLS310D –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
DESIGN EXAMPLE
• Input Voltage: 10 Vdc to 24 Vdc
• Output voltage: 3.3 V +2% (3.234 ≤ V
O
≤ 3.366)
• Output current: 8 A (maximum, steady state), 10 A (surge, 10-ms duration, 10% duty cycle maximum)
• Output ripple: 33 mVP-P at 8 A
• Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A
• Operating temperature: -40°C to 85°C
• f
SW
= 300 kHz
1. Calculate maximum and minimum duty cycles
(46)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET (t
ON
) must be greater
than 300 ns (see the Electrical Characteristics table). Therefore,
(47)
(48)
Using 400 ns to provide margin,
(49)
Since the oscillator can vary by 10%, decrease f
SW
by 10%
(50)
and therefore choose a frequency of 300 kHz.
3. Select ΔI
In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.
(51)
4. Calculate the power losses
Power losses in the high-side MOSFET (Si7860DP) at 24-V
IN
where switching losses dominate can be calculated
from Equation 52.
(52)
substituting Equation 34 into Equation 33 yields
(53)
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