Datasheet

TPS40055-EP

www.ti.com

SGLS310D –JULY 2005–REVISED FEBRUARY 2012

Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently

small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is

needed to prevent wicking the solder away from the interface between the package body and the solder-tinned

area under the device during solder reflow. Drill diameters of 0,33 mm (13 mils) works well when 1-oz copper is

plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not

plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a

diameter equal to the via diameter of 0,1 mm minimum. This capping prevents the solder from being wicked

through the thermal vias and potentially creating a solder void under the package. See the PowerPAD Thermally

Enhanced Package and the mechanical illustration at the end of this document for more information on the

PowerPAD package.

Figure 17. PowerPAD Dimensions

MOSFET PACKAGING

MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In

general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θ

)

and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on

proper layout and thermal management. The θ

specified in the MOSFET data sheet refers to a given copper

area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce

copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. See

the selected MOSFET's data sheet for more information regarding proper mounting.

GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS

The TPS40055 provides separate signal ground (SGND) and power ground (PGND) pins. It is important that

circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if

possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling

capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.

Sensitive nodes such as the FB resistor divider, R

, and ILIM should be connected to the SGND plane. The

SGND plane should only make a single point connection to the PGND plane.

Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to

their respective power and ground pins. Also, sensitive circuits such as FB, RT, and ILIM should not be located

near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).

Product Folder Link(s): TPS40055-EP