Datasheet

TPS40055-EP
SGLS310D –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
Calculate the Poles and Zeros
For a buck converter using voltage mode control, there is a double pole due to the output L-C
O
. The double pole
is located at the frequency calculated in Equation 21.
(21)
There is also a zero created by the output capacitance (C
O
) and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 22.
(22)
Calculate the value of R
BIAS
to set the output voltage (V
OUT
).
(23)
The maximum crossover frequency (0 dB loop gain) is calculated in Equation 24.
(24)
Typically, f
C
is selected to be close to the midpoint between the L-C
O
double pole and the ESR zero. At this
frequency, the control to output gain has a -2 slope (–40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 13 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
MODULATOR GAIN
vs
SWITCHING FREQUENCY
Figure 12. PWM Modulator Relationships Figure 13.
A Type III topology, shown in Figure 14, has 2 zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 15. The two zeros are used to compensate the L-C
O
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases, the second pole can be eliminated and the amplifier's gain roll-off used to
roll-off the overall gain at higher frequencies. Figure 14.
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