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TPS40055-EP

www.ti.com

SGLS310D –JULY 2005–REVISED FEBRUARY 2012

WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS40055-EP

FEATURES

APPLICATIONS

• Operating Input Voltage 8 V to 40 V

• Power Modules

• Input Voltage Feed-Forward Compensation • Networking/Telecom

• < 1 % Internal 0.7-V Reference • Industrial/Servers

• Programmable Fixed-Frequency Up to 1-MHz

DESCRIPTION

Voltage Mode Controller

The TPS40055 is a family of high-voltage, wide input

• Internal Gate Drive Outputs for High-Side and

(8 V to 40 V), synchronous, step-down converters.

Synchronous N-Channel MOSFETs

The TPS40055 family offers design flexibility with a

• 16-Pin PowerPAD™ Package (θ

= 25°C/W)

variety of user programmable functions, including

soft-start, UVLO, operating frequency, voltage feed-

• Thermal Shutdown

forward, high-side current limit, and loop

• Externally Synchronizable

compensation.

• Programmable High-Side Sense Short-Circuit

The TPS40055 are also synchronizable to an external

Protection

supply. The TPS40055 incorporates MOSFET gate

• Programmable Closed-Loop Soft-Start

drivers for external N-channel high-side and

• TPS40055 Source/Sink

synchronous rectifier (SR) MOSFETs. Gate drive

logic incorporates anti-cross conduction circuitry to

SUPPORTS DEFENSE, AEROSPACE,

prevent simultaneous high-side and synchronous

rectifier conduction.

AND MEDICAL APPLICATIONS

• Controlled Baseline The TPS40055 uses voltage feed-forward control

techniques to provide good line regulation over the

• One Assembly/Test Site

wide (4:1) input voltage range and fast response to

• One Fabrication Site

input line transients with near constant gain with input

• Available in Military (–55°C/125°C)

variation which eases loop compensation. The

externally programmable current limit provides pulse-

Temperature Range

(1)

by-pulse current limit, as well as a hiccup mode

• Extended Product Life Cycle

operation utilizing an internal fault counter for longer

• Extended Product-Change Notification

duration overloads.

• Product Traceability

(1) Additional temperature ranges available - contact factory

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

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TPS40055-EP 8 www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS40055-EP FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • Operating Input Voltage 8 V to 40 V Input Voltage Feed-Forward Compensation < 1 % Internal 0.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com SIMPLIFIED APPLICATION DIAGRAM TPS40055 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT VIN VIN Input voltage range 45 V VFB, SS, SYNC –0.3 V to 6 V SW –0.3 V to 45 V SW, transient < 50 ns –2.5 V KFF, with IIN(max) = –5 mA –0.3 V to 11 V VOUT Output voltage range COMP, RT, SS –0.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –55°C to 125°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS Maximum duty cycle VFB = 0 V, 500 kHz ≤ fSW ≤ 1 MHz Feed-forward voltage IKFF Feed-forward current operating range (2) TYP 84% (2) MAX UNIT 94% 80% VFB ≥ 0.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 ELECTRICAL CHARACTERISTICS (continued) TA = –55°C to 125°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage, LDRV ILDRV = –0.1 A VOL Low-level output voltage, LDRV ILDRV = 0.1 A MIN TYP BP10 –1.8 BP10 –1 Minimum controllable pulse width MAX UNIT V 0.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com DEVICE INFORMATION (1) For more information on the PWP package, see the Texas Instruments Technical Brief (SLMA002) (2) PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 14 O Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage. A 0.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. SYNC 4 I Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency. If synchronization is not used, connect this pin to SGND. VFB 7 I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage, 0.7 V.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION The TPS40055 allows the user to optimize the PWM controller to the specific application. The TPS40055 is the controller of choice for synchronous buck designs, which includes most applications. It has two quadrant operations and will source or sink output current. This provides the best transient response.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 RT is the timing resistance in kΩ. The curve showing the RKFF required for a given switching frequency (fSW) is shown in Figure 4. For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Figure 5. Undervoltage Lockout Operation The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start up voltage.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 INPUT VOLTAGE vs BP5 VOLTAGE INPUT VOLTAGE vs BP10 VOLTAGE Figure 8. Figure 9. SELECTING THE INDUCTOR VALUE The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in Equation 6.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 + VIN − RA 499 kW RKFF 71.5 kW CA 47 pF 1 KFF ILIM 16 2 RT VIN 15 3 BP5 BOOST 14 4 SYNC HDRV 13 5 SGND SW 12 6 SS BP10 11 7 VFB LDRV 10 8 COMP PGND 9 PWP DA 1N914, 1N4150 Type Signal Diode UDG−03034 Figure 10. Hysteresis for Programmable UVLO Energy in the capacitor is described in Equation 10.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the higher the input current required during start-up. This relationship is describe in more detail in the section titled, Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in Equation 14.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 (16) where: ISINK is the current into the ILIM pin and is 7.5 µA, minimum IOC is the overcurrent setpoint which is the dc output current plus one-half of the peak inductor current VOS is the overcurrent comparator offset and is –20 mV, maximum SYNCHRONIZING TO AN EXTERNAL SUPPLY The TPS40055 can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the falling edge of the SYNC signal.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Calculate the Poles and Zeros For a buck converter using voltage mode control, there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 21. (21) There is also a zero created by the output capacitance (CO) and its associated ESR. The ESR zero is located at the frequency calculated in Equation 22. (22) Calculate the value of RBIAS to set the output voltage (VOUT).
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 Figure 14. Type III Compensation Configuration Figure 15. Type III Compensation Gain and Phase The poles and zeros for a Type III network are described in Equation 25. (25) The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and 100 kΩ usually yields reasonable values. The unity gain frequency is described in Equation 26. (26) where G is the reciprocal of the modulator gain at fC.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 30. (30) dv/dt INDUCED TURN-ON MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 ID2 } IO ID1 d BODY DIODE CONDUCTION ∆I 1−d BODY DIODE CONDUCTION SW 0 ANTI−CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON HIGH SIDE ON UDG−02139 Figure 16. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by Equation 34. (34) where: (35) and θJA is the package thermal impedance.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com The QRR is not always described in a MOSFET's data sheet, but may be obtained from the MOSFET vendor. The total synchronous rectifier MOSFET power dissipation is described in Equation 39. (39) TPS40055 POWER DISSIPATION The power dissipation in the TPS40055 is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com DESIGN EXAMPLE • • • • • • • Input Voltage: 10 Vdc to 24 Vdc Output voltage: 3.3 V +2% (3.234 ≤ VO ≤ 3.366) Output current: 8 A (maximum, steady state), 10 A (surge, 10-ms duration, 10% duty cycle maximum) Output ripple: 33 mVP-P at 8 A Output load response: 0.3 V => 10% to 90% step load change, from 1 A to 7 A Operating temperature: -40°C to 85°C fSW = 300 kHz 1. Calculate maximum and minimum duty cycles (46) 2.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 and from Equation 33, the switching losses can be determined. (54) The MOSFET junction temperature can be found by substituting Equation 35 into Equation 34 (55) 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two loss components: conduction and diode reverse recovery losses.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 8. Programming the ramp generator circuit The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from Equation 64. W (64) 9. Calculating the output capacitance (CO) In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A to 8-A step load.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 (73) Select the close-loop 0 dB crossover frequency (fC). For this example, fC = 20 kHz. Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz. Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7 kHz.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com (83) For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1-µF capacitor is used for the BP10V bypass.
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TPS40055-EP www.ti.com SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 DESIGN EXAMPLE SUMMARY Figure 18 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST to get sufficient gate drive for the upper MOSFET. As seen in Figure 9, the BP10 output is about 6 V with the input at 8 V, so the upper MOSFET gate drive may be less than 5 V.
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TPS40055-EP SGLS310D – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Revision C (February 2012) to Revision D • 28 Page Changed ISINK current minimum from 8.5 µA to 7.5 µA for equation 16 .............................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS40055MPWPREP Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40055MPWPREP HTSSOP PWP 16 2000 367.0 367.0 35.
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