Datasheet

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Block Diagram
OSCILLATOR
4
VDD
UVLO
2 V
6
8
7
5
VDD
VDD
LDRV
HI
LO
BOOT
HDRV
SW
LDRV
ADAPTIVE
GATE
DRIVE
PWM
LOGIC
2
3
COMP
FB
VDD/2
CURRENT LIMIT
COMP
EN
100ns
DELAY
VREF
RAMP
CLOCK
+
−
+
VDD
PAD
GND
Soft Start
FAULT
LOGIC
SW
Calibration
Circuit
ILIM SET
ILIM SET
SDN
CLOCK
Reference
VREF
ILIM voltages
105 mV
180 mV
310 mV
VDD
Pre−bias
Thermal
Shutdown
1
Vdd−1.2v
EN
PWM COMP
0.6V
SDN
100K
PWM
0.6 V
TPS40040 , TPS40041
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
Figure 18. Functional Block Diagram
Copyright © 2006 – 2007, Texas Instruments Incorporated 9
Product Folder Link(s): TPS40040 TPS40041