Datasheet

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DEVICE INFORMATION
TERMINAL CONFIGURATION
1
2
3
EN
FB
COMP
VDD
HDRV
SW
BOOT
LDRV
5
4
7
8
GND
TPS40040/1
6
TPS40040 , TPS40041
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
The package is an 8-pin SON (DRB) package. Note: The thermal pad is an electrical ground connection.
Figure 17. DRB Package Terminal Configuration (Top View)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
Input (bootstrapped) supply to the high-side gate driver for PWM enabling the gate of the
high side FET to be driven above the input supply rail. Connect a ceramic capacitor from this
pin to SW. This capacitor is charged from the VDD pin voltage through an internal switch.
BOOT 6 I
The switch is turned ON during the off time of the converter. To slow down the turn on of the
external MOSFET, a small resistor (1 Ω to 3 Ω ) may be placed in series with the bootstrap
capacitor. See Applications Section to calculate the appropriate value.
Output of the error amplifier and connection node for loop feedback components. The
voltage at this pin determines the duty cycle for the PWM. Optionally, a resistor from this pin
to ground is used to determine the voltage threshold used for short circuit protection. (See
Application Section)
COMP 3 O
• Low threshold R = 2.4 k Ω , +/-10%
• Mid threshold R = not installed
• High threshold R = 12 k Ω , +/-10%
Active low enable input allows ON/OFF operation of the controller. If power is applied to the
TPS40040/1 while the EN pin is allowed to float high, the TPS40040/1 remains disabled
EN 1 I (both external switches are held OFF). Only when the EN pin is pulled to 1.2 V below VDD is
the TPS40040/1 allowed to start. An internal 100-k Ω resistor is connected between VDD and
EN to provide pull up. Connect this pin to GND to bypass the enable function.
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is at the
internal reference level of 600 mV. A series resistor divider from the converter output to
FB 2 I
ground, with the center connection tied to this pin, determines the value of the regulated
output voltage. This pin is also a connection node for loop feedback components.
This is the gate drive output for the high side N-channel MOSFET switch for PWM. It is
HDRV 8 O
referenced to SW and is bootstrapped for enhancement of the high-side switch.
LDRV 5 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET.
Power input to the device. This pin should be locally bypassed to GND with a low ESR
VDD 4 I
ceramic capacitor of 1 µ F or greater.
Connection to the switched node of the converter and the power return for the upper gate
driver. There should be a high current return path from the source of the upper MOSFET to
SW 7 O
this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between
upper and lower MOSFET conduction.
Ground connection to the device. This is also the thermal pad used to conduct heat from the
device. This connection serves a twofold purpose. The first is to provide an electrical ground
GND Thermal Pad connection for the device. The second is to provide a low thermal impedance path from the
device die to the PCB. This pad should be tied externally to a ground plane. See Application
Section for PC board layout information.
8 Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40040 TPS40041