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Feedback Loop Design
Modeling the Power Stage
A
MOD
+
V
IN
V
RAMP(p*p)
(22)
F
RES
+
1
2 p L C
Ǹ
(23)
F
ESR
+
1
2 p C
OUT
R
ESR
(24)
A
MOD
0dB
F
RES
F
ESR
−40dB/dec
−20dB/dec
Frequency (Log Scale)
Feedback Divider (R4, R5 & R8)
R5 in paralell with R4 +
V
FB
R8
V
OUT
* V
FB
(25)
TPS40040 , TPS40041
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
To design feedback circuit, a small signal average modeling technique is employed. Further information on this
technique may be found in the references.
The peak-to-peak ramp voltage given in the Electrical Specification table allows the modulator gain to be
calculated as:
For this design, a modulator gain of 7.3 (17.3 dB) is calculated.
The LC filter applies a double pole at the resonance frequency:
For this design, the resonance frequency is about 11.3 kHz. Below this frequency, the power stage has the dc
gain of 17.3 dB and above this frequency the power stage gain drops off at -40 dB per decade. The ESR zero is
approximated by:
For C
OUT
= 2 x 100 µ F and R
ESR
= 2.5 m Ω F
ESR
= 318 kHz. This is greater than 1/5th the switching frequency
and outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per
decade above F
ESR
. The straight line approximation the power stage gain is approximated in Figure 24 .
Figure 24. Power Stage Frequency Response Straight Line Approximation
Select R8 be between 10 k Ω and 100 k Ω . For this design, select 20 k Ω . Next, R5 is selected to produce the
desired output voltage when V
FB
= 0.600 V using the following formula.
VFB = 0.600 V and R8 = 20 k Ω for VOUT = 1.8 V, R5 = 10 k Ω . If the calculated value is not a standard resistor,
select a slightly higher resistor value and add R4 in parallel to reduce the parallel combination of R4 and R5 to
produce desired output voltage.
24 Copyright © 2006 – 2007, Texas Instruments Incorporated
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