Datasheet

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Bootstrap Capacitor (C7)
C
BOOST
+
20 Q
GS_Q1
V
IN(min)
(19)
VDD Bypass Capacitor (C6)
VDD Filter Resistor (R7)
R
VDD
t
V
RVDD(max)
I
DD
+
25 mV
2 mA )
ǒ
Q
G_Q1
) Q
G_Q2
Ǔ
F
SW
(20)
Short Circuit Protection (R2)
V
CS
+ I
L(peak)
R
DS(on_Q1)
(21)
TPS40040 , TPS40041
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
To ensure proper charging of the upper switch MOSFET gate, limit the ripple voltage on the bootstrap capacitor
to < 5% of the minimum gate drive voltage of 3.0 V.
Based on the IRF7910 MOSFET with a maximum total gate charge of 26 nC, calculate a minimum of 116 nF of
capacitance. The next higher standard value of 220 nF is selected.
Select a 1.0- µ F ceramic bypass capacitor for VDD.
An optional resistor in series with VDD helps filter switching noise from the device. Driving the two IRF7910
MOSFETs, with a typical total Q
G
of 17 nC each, we calculate a maximum I
DD
current of 22 mA. The result of
equation 19, leads to selecting a 1- Ω resistor, and limits the voltage drop across this resistor to less than 25 mV.
The TPS40040/1 use the forward drop across the upper switch MOSFET during the ON time to measure the
inductor current. The voltage drop across the high-side MOSFET is given by:
When V
IN
= 4.5 V to 5.5 V, I
L_PEAK
= 7.2A. Using the IRF7910 MOSFET, we calculate the peak voltage drop to
be 108 mV. The TPS40041 ’ s internal 3100-ppm temperature coefficient helps compensate for the MOSFET ’ s
R
DS(on)
temperature coefficient. For this design, select the short circuit protection voltage threshold of 180 mV by
selecting R2 = OPEN.
Copyright © 2006 – 2007, Texas Instruments Incorporated 23
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