Datasheet
www.ti.com
MOSFET Switch Selection (Q1 & Q2)
P
G1SW
+
1
2
V
IN
I
OUT
ǒ
T
RISE
) T
FALL
Ǔ
F
SW
+ V
IN
I
OUT
Q
GS2_Q1
) Q
GD_Q1
V
DD
*V
TH
R
DRIVE
F
SW
(14)
Q
GS2_Q1
) Q
GD_Q1
t
P
G1SW
V
IN
I
OUT
V
DD
* V
t
R
DRIVE
1
F
SW
(15)
P
CON_Q1
+ D
ƪ
ǒ
I
OUT
Ǔ
2
)
1
12
ǒ
I
RIPPLE
Ǔ
2
ƫ
R
DS(on)
+
V
OUT
V
IN
I
L(rms)
2
R
DS(on_Q1)
(16)
R
DS(on_Q1)
+
P
CON_Q1
I
L(rms)
2
V
OUT
V
IN
(17)
R
DS(on_Q2)
+
P
CON_Q2
I
L(rms)
2
ǒ
1 *
V
OUT
V
IN
Ǔ
(18)
TPS40040 , TPS40041
SLUS700D – MARCH 2006 – REVISED DECEMBER 2007
The switching losses for the upper switch MOSFET are estimated by:
For this design, switching losses are higher at low input voltage due to the lower gate drive current. Designing for
1 W of total losses in both MOSFETS and 20% of the total MOSFET losses in switching losses, we can estimate
our maximum gate-to-drain charge for the design at:
For a low-gate threshold MOSFET, and the TPS40041 ’ s 5 Ω and 3 Ω drive resistances, we estimate a maximum
Q
GS2
+Q
GD
of 10.8 nC.
The conduction losses in the upper switch MOSFET are estimated by the RMS current through the MOSFET
times its R
DS(on)
:
Estimating about 30% of total MOSFET losses to be high-side conduction losses, the maximum R
DS(on)
of the
high-side MOSFET can be estimated by:
For this design, with I
L_RMS
= 6 A
RMS
and 4.5 V to 1.8 V, R
DS(on_Q1)
is < 19.5 m Ω for the upper switch MOSFET.
Estimating 50% of total MOSFET losses are in the SR as conduction losses, repeat equation 14. Then calculate
the maximum R
DS(on)
of the SR by the equation:
For this design I
L_RMS
= 6 A at 5.5 V to 1.8 V R
DS(on_Q2)
< 19.6 m Ω . The table below summarizes the MOSFET
requirements.
MOSFET Requirements
PARAMETER SYMBOL VALUE UNITS
High-side FET R
DS(on)
R
DS(on_Q1)
19.5 m Ω
High-side FET turn-on charge Q
GS2_Q1
+Q
GD_Q1
10.8 nC
Low-side FET R
DS(on)
R
DS(on_Q2)
19.6 m Ω
IRF7910 has an R
DSON(max)
of 15 m Ω at 4.5-V gate drive,Q
GD
of 6.2 nC, and Q
GS2
of 2 nC.
22 Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40040 TPS40041