Datasheet

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Gate Drive Resistors

Total Gate Charge

Synchronous Rectifier dV/dt Turn-On

TPS40040 , TPS40041

SLUS700D – MARCH 2006 – REVISED DECEMBER 2007

The TPS40040/41 ’ s adaptive gate delay circuitry monitors the HDRV-to-SW and LDRV-to-GND voltages to

determine the state of the external MOSFET switches. Any voltage drop across an external series gate drive

resistor is sensed as reduced gate voltage during turn-off and may interfere with the MOSFET timing.

DESIGN A resistor should never be placed in series with the synchronous rectifiers gate

HINT: and the gate trace should be kept as short as practical in the layout.

The internal voltage sensing of the external MOSFET gate voltages used by the TPS40040/1 to control the

dead-times between turn-off and turn-on can be sensitive to large MOSFET gate charges, especially when

different gate charges are used for the high-side and low-side MOSFETs. Increased gate charge increases

MOSFET switching times and decreases the dead-time between the MOSFETs switching.

MOSFETs with no more than 40 nC of total gate charge should be selected.

DESIGN The upper switch MOSFET ’ s gate charge should be no less than 60% of the

HINT: synchronous rectifier ’ s gate charge to minimize the turn-on/turn-off delay

mismatch between the high-side and low-side MOSFET.

As the upper switch MOSFET turns on, the switch node voltage rises from close to ground to VIN in a very short

period of time (typically 10 ns to 30 ns) resulting in very high voltage spikes on the switch node. The construction

of a MOSFET creates parasitic capacitances between its terminals, particularly the gate-to-drain and

gate-to-source, creating a capacitive divider between the drain and source of the MOSFET with the gate at its

mid-point. If the gate-to-drain charge (Q

) is larger than the gate-to-source charge (Q

), the capacitive divider

places proportionally more charge on the gate of the MOSFET as the switch node voltage rises than is shunted

to GND. In extreme cases, this can cause the synchronous rectifier gate voltage to rise above the turn on

threshold voltage of the MOSFET and causes cross-conduction. This is called dV/dt turn-on. It increases power

dissipation in both the high-side and the low-side MOSFET, reducing efficiency.

Select a synchronous rectifier MOSFET with a Q

to Q

ratio of less than

DESIGN

one and provide a wide, low resistance, low inductance loop in the synchronous

HINT:

rectifier gate drive circuit. (See Layout Consideration)

A resistor in series with the boost capacitor slows the turn on of the high-side

DESIGN

MOSFET, and reduces the dV/dt of the switch node. See Boost Capacitor

HINT:

Series Resistor section.

Product Folder Link(s): TPS40040 TPS40041