User’s Guide TPS40007-Based Converter Delivers 10-A Output User’s Guide
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 VDC to 5.5 VDC. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
SLUU188 − March 2004 TPS40007-Based Converter Delivers 10-A Output Mark Dennis DC to DC Controller Products Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Schematic . . . . . . . . . . . . . . . . . . . . . . . .
SLUU188 − March 2004 + + + Schematic + 3 Figure 1.
SLUU188 − March 2004 4 Design Procedure 4.1 Controller Selection The TPS40007 synchronous buck controller is selected for this high-current application because the 300-kHz switching frequency enables higher efficiency. The TPS40009 is available for applications needing 600-kHz operation for reducing component size. However, at higher frequency the efficiency is generally reduced, leading to more on-board power dissipation. 4.
SLUU188 − March 2004 4.4 Output Capacitor Selection Selection of the output capacitor is based on many application variables, including function, cost, size, and availability. First, the minimum allowable output capacitance should be determined by the amount of inductor ripple current and one-half the allowable output ripple, as given in equation (4). C OUT(min) + I RIPPLE + 8 f V RIPPLE 8 4A 300 kHz 25 mV + 67 mF (4) This only affects the capacitive component of the ripple voltage.
SLUU188 − March 2004 4.7 Compensation Design The TPS40007 uses voltage mode control in conjunction with a high frequency error amplifier. The power circuit L-C double pole corner frequency fC is located in equation (7). Freq LC + 1 2 ǸL OUT p C OUT + 5.1 kHz (7) The output capacitor ESR zero is calculated by equation (8), F Z(esr) + 2 p 1 R ESR C OUT + 33.
SLUU188 − March 2004 Figure 2 is presents the measured loop gain and phase characteristics. At the loop crossover frequency of 20 kHz the phase margin is approximately 50 degrees. GAIN AND PHASE MARGIN vs FREQUENCY 30 200 50 150 40 Phase 100 20 50 10 0 0 Gain −50 Phase − degrees Gain − db 30 −10 −100 −20 −150 −30 −40 100 −200 1000 10000 100000 1000000 Frequency − Hz Figure 2. 4.8 Snubber Component Selection The switch node where Q1 and L1 come together is very noisy.
SLUU188 − March 2004 5 PowerPAD] Packaging The TPS4000X family is available in the DGQ version of TI’s PowerPADt thermally enhanced package. In the PowerPADt, a thermally conductive epoxy is utilized to attach the integrated circuit die to the leadframe die pad, which is exposed on the bottom of the completed package. The leadframe die pad can be soldered to the PCB using standard solder flow techniques when maximum heat dissipation is required.
SLUU188 − March 2004 6 Test Results/Performance Data 6.1 Test Setup dc power supply adjustable from 0 V to 5 V DVM1 Input wires 16 gauge or larger, as short as feasible (+) IIN (−) J1 HPA068 VIN GND TP3 TP1 TP4 TP2 SCOPE TP7 TP6 VOUT GND TP5 J2 Output wires 16 gauge or larger, as short as feasible DVM2 (+) IOUT (−) (−) LOAD (+) Load adjustable from 0−10Amps Figure 4.
SLUU188 − March 2004 Typical efficiency curves are shown in Figure 5 for 3.3-V input. It should be stressed that measuring high efficiencies requires the utmost care in instrumentation. The power losses are so low that small errors can lead to large variations in measured efficiency. The input and output voltages are measured on the PCB as shown in the test diagram to avoid the losses associated with the input and output connectors.
SLUU188 − March 2004 Figure 7 shows the output voltage ripple at high VIN and full load, which is the worst case condition for output voltage ripple. OUTPUT VOLTAGE RIPPLE 10 mV/div t − Time − 1 µs/div Figure 7. Figure 8 shows the transient response with a 50% load step from 2.5 A to 7.5 A. TRANSIENT RESPONSE 50 mV/div t − Time − 20 µs/div Figure 8.
SLUU188 − March 2004 7 PCB Layout The PCB top assembly and copper layers are shown in Figures 9 through 11.
SLUU188 − March 2004 8 List of Material Table 1 lists the components used in this design. With minor component tweaks this design could be modified to meet a wide range of applications. Reference Qty Description Manufacturer Part Number C1, C2 2 POSCAP, 330 µF, 6.3 V, 10 milliohm, 20%, 7343 (D) Sanyo 6TPD330M C11 1 Ceramic, 180 pF, 50 V, NPO, 10%, 805 Vishay VJ0805A181KXAAT C12 1 Ceramic, 0.01µF, 50 V, X7R, 10%, 805 Vishay VJ0805Y103KXAAT C13 1 Ceramic, 0.
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