Datasheet

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
5
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
BOOT 10 O
Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
MOSFET to be driven above the input supply rail
COMP 3 O Output of the error amplifier
FB 2 I Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.
GND 5 −
Power supply return for the device. The power stage ground return on the board requires a separate path from other
sensitive signal ground returns.
HDRV 9 O
This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2 × V
DD
for good en-
hancement of the topside MOSFET.
ILIM 1 I
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-µA current sink at
the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the
top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the
first 100 ns to allow full enhancement of the top MOSFET. Set the ILIM voltage level such that it is within 800 mV of
V
DD
; that is, (V
DD
− 0.8) ≤ I
ILIM
≤ V
DD
.
LDRV 6 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET
SS/SD 4 I
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.
A closed loop soft-start occurs when the internal 3-µA current source charges the external capacitor. There is a 0.65-V
offset between external SS pin and internal soft-start voltage at the error amplifier input. This allows the device to be
enabled before starting V
OUT
, thus ensuring that V
OUT
soft starts smoothly. When the SS/SD voltage is less than 0.25
V, the device is shutdown and the HDRV and LDRV are driven low. In normal operation, the capacitor is charged to
VDD. When a fault condition is asserted, the soft-start capacitor goes through six charge/discharge cycles, restarting
the converter on the seventh cycle.
SW 8 O
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel
MOSFET, and level sensing for predictive delay circuit. Overcurrent is determined, when the topside N-channel MOS-
FET is on, by comparing the voltage on SW with respect to VDD and the voltage on the ILIM with respect to VDD.
This pin is also used for the return of the topside N-channel MOSFET driver.
VDD 7 I Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or larger.
FUNCTIONAL BLOCK DIAGRAM
UDG−031
62
15 µA
3.7 µA
7
BOO
T
10
VDD
2
ILIM
1
FB
3
SW
8
C
OMP
4
HDR
V
9
S
S/SD
5
LDR
V
6
GND
UVLO
VDD
+
REF
2 V
ERROR AMPLIFIER
0.7 V
SOFT
START
0.26 V
SHUT DOWN
OSC
UVLO
DISCHARGE
SS ACTIVE
FAULT
COUNTER
PWM COMP
PWM
LOGIC
OC
THERMAL
SHUTDOWN
CLK
UVLO
PREDICTIVE
GATE
DRIVE
(VDD−1.2 V)
CURRENT
LIMIT COMP
VDD
PWM
LO
VDD
HI
FAULT
LDRV
100 ns DELAY
EN
0.65 V
+