Datasheet
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005
4
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ELECTRICAL CHARACTERISTICS
temperature range, T
A
= −40_C to 85_C, V
DD
= 5.0 V, T
A
= T
J
; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVER
R
HDHI
HDRV pull-up resistance
V
BOOT
−V
SW
= 3.3 V
,
I
SOURCE
= −100 mA
3 5.5
R
HDLO
HDRV pull-down resistance
V
BOOT
− V
SW
= 3.3 V
,
I
SINK
= 100 mA
1.5 3
Ω
R
LDHI
LDRV pull-up resistance V
DD
= 3.3 V, I
SOURCE
= −100 mA 3 5.5
R
LDLO
LDRV pull-down resistance V
DD
= 3.3 V, I
SINK
= 100 mA 1.0 2.0
t
RLD
LDRV rise time 15 35
t
FLD
LDRV fall time
C
LOAD
= 1 nF
10 25
ns
t
RHD
HDRV rise time
C
LOAD
= 1 nF
15 35
ns
t
FHD
HDRV fall time 10 25
PREDICTIVE DELAY
V
SWP
Sense threshold to modulate delay time −350 mV
T
LDHD
Maximum delay modulation range time LDRV OFF − to − HDRV ON 45 70 95
Predictive counter delay time per bit LDRV OFF − to − HDRV ON 2.8 4.3 6.2
ns
T
HDLD
Maximum delay modulation range HDRV OFF − to − LDRV ON 50 80 110
ns
Predictive counter delay time per bit HDRV OFF − to − LDRV ON 3.0 4.8 6.6
SHUTDOWN
V
SD
Shutdown threshold voltage Outputs OFF 0.21 0.26 0.31
V
V
EN
Device active threshold voltage 0.25 0.29 0.35
V
SOFTSTART
I
SS
Soft-start source current Outputs OFF 2.0 3.7 5.4 µA
V
SS
Soft-start voltage to begin V
OUT
start 0.35 0.65 0.95 V
BOOTSTRAP
R
BOOT
Bootstrap switch resistance
V
DD
= 3.3 V 50 100
Ω
R
BOOT
Bootstrap switch resistance
V
DD
= 5 V
35 70
Ω
V
OUT
PRE-BIAS
Recommended VOUT pre-bias level as
% of final regulation
(1)(4)
FB percent of 700 mV 90%
SW NODE
I
SW
Leakage current in shutdown 2 µA
THERMAL SHUTDOWN
t
SD
Shutdown temperature
(1)
165
°C
Restart from thermal shutdown
(1)
−15
°C
(1)
Ensured by design. Not production tested.
(2)
Derate the maximum duty cycle by 3% for V
DD
< 3 V.
(3)
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
(4)
Prebiased output greater than 90% of final regulation may lead to sinking current from the prebias output.