Datasheet

 
 
 
SLUS507D − JANUARY 2002 − REVISED NOVEMBER 2005
7
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functional block diagram
UDG−01142
15 µA
3 µA
7
BOOT
10
VDD
ILIM
1
3
SW
8
COMP
4
HDRV9
SS/SD
5
LDRV
6
GND
UVLO
VDD
2 V
SOFT
START
0.12 V
SHUT DOWN
OSC
UVLO
DISCHARGE
SS ACTIVE
FAULT
COUNTER
PWM COMP
PWM
LOGIC
OC
THERMAL
SHUTDOWN
CLK
UVLO
PREDICTIVE
GATE
DRIVE
(VDD−1.2 V)
CURRENT
LIMIT COMP
LDRV
RECTIFIER
ZERO−CURRENT
COMPARATOR
VDD
PWM
LO
VDD
HI
FAULT
LDRV
100 ns DELAY
EN
EN
75 ns
DELAY
2FB
+
REF
ERROR AMPLIFIER
0.7 V
+