Datasheet
SLUS507D − JANUARY 2002 − REVISED NOVEMBER 2005
12
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APPLICATION INFORMATION
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (V
CSS
) begins to ramp up
and acts as the reference until it passes the internal reference voltage at t1. At this point the soft-start period
is over and the converter is regulating its output at the desired voltage level. From t0 to t1, pulse-by-pulse current
limiting is in effect, and from t1 onward, overcurrent pulses are counted for purposes of determining a possible
fault condition. At t2, a heavy overload is applied to the converter. This overload is in excess of the overcurrent
threshold. The converter starts limiting current and the output voltage falls to some level depending on the
overload applied. During the period from t2 to t3, the counter is counting overcurrent pulses, and at time t3
reaches a full count of 7. The soft-start capacitor is then discharged, the counter is decremented, and a fault
condition is declared.
V
CSS
V
OUT
I
LOAD
UDG−01144
t
t0 t1 t2 t3 t10
0 6 5 4 3 2 1 0
t4
t5 t6 t7 t8 t9
1 2 3 4 5 6 7
0.7 V
FAULT
Figure 4. Switch Node Waveforms for Synchronous Buck Converter
When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3-µA current source. As the capacitor voltage reaches full charge, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been
decremented to 0. The fault logic is then cleared, the outputs are enabled, and the converter attempts to restart
with a full soft-start cycle. The converter comes into regulation at t10.