Datasheet

SENSE4
SENSE3
SENSE2
SENSE1
VCC
/MR
/RESET
GND
MSOP-8
1
2
3
4
8
7
6
5
TPS386596L33
www.ti.com SLVSA75 –JULY 2010
DEVICE INFORMATION
PIN CONFIGURATION
PIN FUNCTIONS
PIN
DESCRIPTION
NAME NO.
SENSE1 4 Monitor voltage input for Supply 1 When the voltage at this terminal drops below the threshold voltage (VIT1=
2.9V), RESET is asserted.
SENSE2 3 Monitor voltage input for Supply 2 When the voltage at this terminal drops below the threshold voltage (VIT2=
0.4V), RESET is asserted.
SENSE3 2 Monitor voltage input for Supply 3 When the voltage at this terminal drops below the threshold voltage (VIT3=
0.4V), RESET is asserted.
SENSE4 1 Monitor voltage input for Supply 4 When the voltage at this terminal drops below the threshold voltage (VIT4=
0.4V), RESET is asserted.
MR 7 Manual reset input with internal 100k pull-up to Vcc and 50ns deglitch. Logic low level of this pin asserts RESET.
RESET 6 RESET is an open-drain output pin. When RESET is asserted, this pin remains in a low-impedance state. When
RESET is released, this pin goes to a high-impedance state after 50ms.
Vcc 8 Supply voltage. Connecting a 0.1 µF ceramic capacitor close to this pin is recommended.
GND 5 Ground
GENERAL DESCRIPTION
The TPS386596L33 multi-channel reset supervisor provides a complete single reset function for a four power
supply system. The design of the SVS is based on the TPS386000 quad supervisor device series. TPS386596 is
designed to assert the /RESET signal following the logic in Table 1. The RESET output remains asserted for a
50ms delay time after the event of reset release. The SENSE1 input has a fixed voltage threshold designed to
monitor a 3.3V nominal supply. The trip point, V
IT1
, for SENSE1 is 2.90 (TYP). Each of the remaining SENSEn
inputs (n = 2,3,4) can be set to any voltage threshold above 0.4V using an external resistor divider. An active low
manual reset (MR) input is also provided for asserting the RESET signal as desired by the system.
RESET OUTPUT
In a typical application of TPS386596, the RESET output is connected to the reset input of a processor (DSP,
MCU, CPU, FPGA, ASIC, etc.) or connected to the enable input of voltage regulators (DC-DC, LDO, etc.).
TPS386596 provides an open drain reset output. Pull-up resistors must be used to hold this line high when
RESET is not asserted. By connecting a pull-up resistor to the proper voltage rail (up to 6.5V), the RESET output
can be connected to other devices at the right interface voltage level. The pull-up resistor should be no smaller
than 10kΩ as a result of the finite impedance of the output transistor.
The RESET output is defined for VCC > 0.9V. To ensure that the target processor is properly reset, the VCC
supply input should be fed by the power rail which is available as early as possible in the application.
Table 1 describes a truth table of how the RESET output is asserted or released. Figure 3 provides a timing
diagram that shows how RESET is asserted and de-asserted in relation to MR and the SENSEn inputs. Once the
conditions are met, the transitions from the asserted state to the release state are performed after a fixed 50ms
delay time.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS386596L33