Datasheet
TPS3836E18-Q1 / J25-Q1 / H30-Q1 / L30-Q1 / K33-Q1
TPS3837E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1, TPS3838E18-Q1 / J25-Q1 / L30-Q1 / K33-Q1
NANOPOWER SUPERVISORY CIRCUITS
SGLS141A − DECEMBER 2002 − REVISED JANUARY 2007
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITION MIN
TYP
MAX UNIT
RESET
V
DD
= 3.3 V, I
OH
= −2 mA
V
High level output voltage
RESET
(TPS3836)
V
DD
= 6 V, I
OH
= −3 mA
0.8 ×
V
V
OH
High-level output voltage
RESET
V
DD
= 1.8 V, I
OH
= −1 mA
0
.
8
×
V
DD
V
RESET
(TPS3837)
V
DD
= 3.3 V, I
OL
= −2 mA
RESET
V
DD
= 1.8 V, I
OL
= 1 mA
V
Low level output voltage
RESET
(TPS3836/8)
V
DD
= 3.3 V, I
OL
= 2 mA
04
V
V
OL
Low-level output voltage
RESET
V
DD
= 3.3 V, I
OL
= 2 mA
0.4 V
RESET
(TPS3837)
V
DD
= 6 V, I
OL
= 3 mA
Power up reset voltage
TPS3836/8 V
DD
≥ 1.1 V, I
OL
= 50 µA 0.2
Power-up reset voltage
(see Note 2)
TPS3837 V
DD
≥ 1.1 V, I
OH
= −50 µA
0.8 ×
V
DD
V
TPS383xE18 1.64 1.71 1.76
Nti iitthhld
TPS383xJ25 2.16 2.25 2.30
V
IT
Negative-going input threshold
voltage (see Note 3)
TPS383xH30 2.70 2.79 2.85
V
V
IT
vo
lt
age
(
see
N
o
t
e
3)
TPS383xL30 2.54 2.64 2.71
V
TPS383xK33 2.82 2.93 3.10
1.7 V < V
IT
< 2.5 V 30
V
h
y
s
Hysteresis at V
DD
input
2.5 V < V
IT
< 3.5 V 40
mV
V
hys
Hysteresis
at
V
DD
input
3.5 V < V
IT
< 5 V 50
mV
I
IH
Hi
g
h-level input current
MR
(see Note 4)
MR = 0.7 × V
DD
, V
DD
= 6 V −40 −60 −100 µA
I
IH
High level
input
current
CT CT = V
DD
= 6 V −25 25 nA
I
IL
Low-level input current
MR
(see Note 4)
MR = 0 V, V
DD
= 6 V −130 −200 −340 µA
I
IL
Low level
input
current
CT CT = 0 V, V
DD
= 6 V −25 25 nA
I
OH
High-level output current TPS3838 V
DD
= V
IT
+ 0.2 V, V
OH
= V
DD
25 nA
V
DD
> V
IT
, V
DD
< 3 V 220 500
nA
I
DD
Supply current
V
DD
> V
IT
, V
DD
> 3 V 250 550
nA
I
DD
Supply
current
V
DD
< V
IT
10 25 µA
Internal pullup resistor at MR 30 kΩ
C
I
Input capacitance at MR, CT V
I
= 0 V to V
DD
5 pF
NOTES: 2. The lowest voltage at which RESET output becomes active. t
r,
V
DD
≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
4. If manual reset is unused, MR
should be connected to V
DD
to minimize current consumption.