Datasheet

V
DD
t
d
t
d
t
d
V
IT
1.1 V
RESET
Output Condition
Undefined
WDI
1st Window
Without Lower
Boundary
2nd Window
With Lower
Boundary
3rd Window
With Lower
Boundary
Trigger Pulse
Lower Window
Boundary
1st Window
Without Lower
Boundary
1st Window
Without Lower
Boundary
2nd Window
With Lower
Boundary
3rd Window
With Lower
Boundary
t
t
t
Output Condition
Undefined
RESET
WDT
_
+
Rising Edge
Detection
Watchdog
Ratio
Detection
Reset Logic
and Timer
Bandgap
Voltage
Reference
Oscillator
Detection
Circuit
WDI
WDR
GND
V
DD
Power to circuitry
GND
R
2
R
1
GND
GND
TPS3813J25, TPS3813L30
TPS3813K33, TPS3813I50
www.ti.com
SLVS331G DECEMBER 2000REVISED OCTOBER 2013
The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same
time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the
different oscillator frequency. This is described in more detail in the following section. The timing diagram and
especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description.
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