Datasheet
SGLS142A − DECEMBER 2002 − REVISED JUNE 2008
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 2.5 V to 6 V, I
OH
= −500 µA V
DD
–0.2
V
OH
High-level output voltage
V
DD
= 3.3 V, I
OH
= −2 mA V
DD
–0.4
V
V
OH
High-level output voltage
V
DD
= 6 V, I
OH
= −4 mA
T
A
= −40°C to 25°C V
DD
–0.4
V
V
DD
= 6 V, I
OH
= −4 mA
T
A
= 125°C V
DD
–0.5
V
DD
= 2 V to 6 V, I
OL
= 500 µA 0.2
V
OL
Low-level output voltage
V
DD
= 3.3 V, I
OL
= 2 mA
0.4
V
V
OL
Low-level output voltage
V
DD
= 6 V, I
OL
= 4 mA 0.4
V
Power-up reset voltage (see Note 2) V
DD
≥ 1.1 V, I
OL
= 50 µA 0.2 V
TPS3809J25 2.20 2.25 2.30
Negative-going input
TPS3809L30
T
A
= −40°C to 125°C
2.58 2.64 2.70
V
IT−
Negative-going input
threshold voltage
(see Note 3)
TPS3809K33
T
A
= −40 C to 125 C
2.87 2.93 2.99
V
V
IT−
threshold voltage
(see Note 3)
TPS3809I50
T
A
= −40°C to 85°C 4.45 4.55 4.65
V
TPS3809I50
T
A
= −40°C to 125°C 4.4 4.55 4.65
TPS3809J25 30
V
hys
Hysteresis
TPS3809L30 35
mV
V
hys
Hysteresis
TPS3809K33
40
mV
TPS3809I50 60
I
DD
Supply current
V
DD
= 2 V, Output unconnected 9 15
A
I
DD
Supply current
V
DD
= 6 V, Output unconnected
20 30
µA
C
i
Input capacitance V
I
= 0 V to V
DD
5 pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. t
r,
VDD
≥ 15 µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1 µF ceramic) should be placed near the supply terminals.
timing requirements at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w
Pulse width at V
DD
V
DD
= V
IT−
+ 0.2 V, V
DD
= V
IT−
− 0.2 V 3 µs
switching characteristics at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d
Delay time
V
DD
≥ V
IT−
+ 0.2 V,
See timing diagram
120 200 280 ms
t
PHL
Propagation (delay) time, high-to-low-level output V
DD
to RESET delay
V
IL
= V
IT−
−0.2 V,
V
IH
= V
IT−
+0.2 V
1 µs