Time
0.8V
0.0V
V
IT
+ V
HYS
V
IT
0.7V
DD
0.3V
DD
MR
SENSE
RESET
V
DD
t
D
t
D
t
D
t
D
= Reset Delay
= Undefined State
TPS3808-Q1
www.ti.com
SBVS085H –JANUARY 2007–REVISED JUNE 2012
Figure 1. MR and SENSE Reset Timing Diagram
TRUTH TABLE
MR SENSE > V
IT
RESET
L 0 L
L 1 L
H 0 L
H 1 H
Copyright © 2007–2012, Texas Instruments Incorporated 5
