Datasheet

TPS3808-Q1
www.ti.com SBVS085H –JANUARY 2007–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS
1.8 V ≤ V
DD
≤ 6.5 V, R
LRESET
= 100 kΩ, C
LRESET
= 50 pF, over operating temperature range (T
J
= –40°C to 125°C) (unless
otherwise noted), typical values at T
J
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
Input supply range 1.8 6.5 V
V
DD
= 3.3 V, RESET not asserted, MR, RESET, C
T
open 2.4 5
I
DD
Supply current (into V
DD
pin) μA
V
DD
= 6.5 V, RESET not asserted, MR, RESET, C
T
open 2.7 6
1.3 V ≤ V
DD
< 1.8 V, I
OL
= 0.4 mA 0.3
V
OL
Low-level output voltage V
1.8 V ≤ V
DD
≤ 6.5 V, I
OL
= 1 mA 0.4
Power-up reset voltage
(1)
V
OL
(max) = 0.2 V, I
RESET
= 15 μA 0.8 V
TPS3808G01 –2 ±1 +2
V
IT
≤ 3.3 V –1.5 ±0.5 +1.5
Negative-going input
V
IT
3.3 V < V
IT
≤ 5 V –2 ±1 +2 %
threshold accuracy
V
IT
≤ 3.3 V –1.25 ±0.5 +1.25
–40°C < T
J
< 85°C
3.3 V < V
IT
≤ 5 V –1.5 ±0.5 +1.5
TPS3808G01 1.5 3
V
HYS
Hysteresis on V
IT
pin –40°C < T
J
< 85°C 1 2 %V
IT
1 2.5
R
MR
MR internal pullup resistance V
SENSE
= V
IT
70 90 kΩ
TPS3808G01 –25 25 nA
I
SENSE
Input current at SENSE pin
V
SENSE
= 6.5 V 1.7 μA
I
OH
RESET leakage current V
RESET
= 6.5 V, RESET not asserted 300 nA
C
T
pin V
IN
= 0 V to V
DD
5
C
IN
Input capacitance, any pin pF
Other pins V
IN
= 0 V to 6.5 V 5
V
IL
MR logic low input 0 0.3 V
DD
V
V
IH
MR logic high input 0.7 V
DD
V
DD
V
SENSE V
IH
= 1.05 V
IT
, V
IL
= 0.95 V
IT
20
t
w
Maximum transient duration μs
MR V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
0.001
C
T
= Open 12 20 28
C
T
= V
DD
180 300 420 ms
t
d
RESET delay time See timing diagram
C
T
= 100 pF 0.75 1.25 1.75
C
T
= 180 nF 0.7 1.2 1.7 s
Propagation delay MR to RESET V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
150 ns
t
pHL
High-level to low-level
SENSE to RESET V
IH
= 1.05 V
IT
, V
IL
= 0.95 V
IT
20 μs
RESET delay
Thermal resistance,
θ
JA
290 °C/W
junction to ambient
(1) Power-up reset voltage is the lowest supply voltage (V
DD
) at which RESET becomes active (t
rise(VDD)
≥ 15 μs/V).
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