Datasheet
Adjustable Voltage Version Fixed Voltage Version
Reset
Logic
Timer
+
−
90k
V
DD
V
DD
GND
0.4V
V
REF
SENSE
MR
C
T
RESET
TPS3808G01
Adjustable Voltage
Reset
Logic
Timer
+
−
90k
V
DD
V
DD
GND
0.4V
V
REF
SENSE
MR
C
T
RESET
R
1
R
2
R
1
+ R
2
= 4M
Ω
PIN ASSIGNMENTS
V
DD
SENSE
C
T
RESET
GND
MR
1
2
3
6
5
4
TPS3808-EP
SBVS103C – APRIL 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Adjustable and Fixed Voltage Versions
DBV PACKAGE
SOT23
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
SOT23 (DBV)
NAME PIN NO. DESCRIPTION
RESET 1 RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (V
IT
) or the MR pin is set to a logic low). RESET remains
low (asserted) for the reset period after both SENSE is above V
IT
and MR is set to a logic high. A pullup
resistor from 10 k Ω to 1 M Ω should be used on this pin, and allows the reset pin to attain voltages higher
than V
DD
.
GND 2 Ground
MR 3 Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to V
DD
by a 90k Ω pullup resistor.
C
T
4 Reset period programming pin. Connecting this pin to V
DD
through a 40-k Ω to 200-k Ω resistor or leaving it
open results in fixed delay times (see Electrical Characteristics ). Connecting this pin to a ground referenced
capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section
for more information.
SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage V
IT
, then RESET is asserted.
V
DD
6 Supply voltage. It is good analog design practice to place a 0.1- µ F ceramic capacitor close to this pin.
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