Datasheet
SLVS184C − NOVEMBER 1998 − REVISED DECEMBER 2005
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
at V
DD
V
DD
= V
IT+
+ 0.2 V, V
DD
= V
IT−
−0.2 V 6 µs
t
w
Pulse width
at MR
V
DD
≥ V
IT+
+ 0.2 V, V
IL
= 0.3 × V
DD
, V
IH
= 0.7 × V
DD
100 ns
t
w
Pulse width
at WDI V
DD
≥ V
IT+
+ 0.2 V, V
IL
= 0.3 × V
DD
, V
IH
= 0.7 × V
DD
100 ns
switching characteristics at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
t(out)
Watchdog time out
V
DD
≥ V
IT+
+ 0.2 V,
See timing diagram
1.1 1.6 2.3 s
t
d
Delay time
V
DD
> V
IT+
+ 0.2 V,
See timing diagram
140 200 280 ms
t
PHL
Propagation (delay) time, high-to-low-level
output
MR to RESET delay
V
DD
≥ V
IT+
+ 0.2 V,
V
IL
= 0.3 × V
DD
50 250
ns
t
PLH
Propagation (delay) time, low-to-high-level
output
MR to RESET delay
(TPS3707−xx only)
DD IT+
V
IL
= 0.3
×
V
DD
V
IH
= 0.7 × V
DD
50 250
ns
t
PHL
Propagation (delay) time, high-to-low-level
output
V
DD
to RESET delay
3 5
s
t
PLH
Propagation (delay) time, low-to-high-level
output
V
DD
to RESET delay
(TPS3707-xx only)
3 5
µs
t
PHL
Propagation (delay) time, high-to-low-level
output
PFI to PFO delay
V
DD
= 2 V to 6 V
0.5 1
s
t
PLH
Propagation (delay) time, low-to-high-level
output
PFI to PFO delay
V
DD
= 2 V to 6 V
0.5 1
µs