Datasheet

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SLVS340D − DECEMBER 2000 − REVISED JULY 2008
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6
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable (CE) signals
prevents erroneous data from corrupting CMOS
RAM during an under-voltage condition. The
TPS3613 uses a series transmission gate from
CEIN to CEOUT. During normal operation (reset
not asserted), the CE transmission gate is
enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay
from CEIN to CEOUT enables the TPS3613
device to be used with most processors.
The CE transmission gate is disabled and CEIN is
in high impedance (disable mode) while reset is
asserted. During a power-down sequence when
V
DD
crosses the reset threshold, the CE
transmission gate is disabled and CEIN
immediately becomes high impedance if the
voltage at CEIN is high. If CEIN is low when reset
is asserted, the CE transmission gate is disabled
when CEIN goes high, or 15 µs after reset asserts,
whichever occurs first. This allows the current
write cycle to complete during power down. When
the CE transmission gate is enabled, the
impedance of CEIN appears as a resistor in series
with the load at CEOUT. The overall device
propagation delay through the CE transmission
gate depends on V
OUT
, the source impedance of
the drive connected to CEIN, and the load at
CEOUT. To achieve minimum propagation delay,
the capacitive load at CEOUT should be
minimized, and a low-output-impedance driver is
used.
In the disabled mode, the transmission gate is off
and an active pullup connects CEOUT to V
OUT
.
This pullup turns off when the transmission gate
is enabled.
15 µs
CEIN
CEOUT
RESET
t
t
t
Figure 2. Chip-Enable Timing