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TEXAS INSTRUMENTS Manuals
PMICs
PMIC - system monitor Reserve capacity circuit VSSOP 10
1
2
3
4
5
6
7
8
9
10
SL
VS340D
−
DECEMBER 2000 − REVISED JUL
Y 2008
www.ti.com
4
TIMING DIAGRAM
V
DD
V
DD
V
BAT
1.
1
V
V
IT
t
t
t
t
t
d
t
d
MR
NOT
E: Sh
aded area
in
R
ESET
is
un
defi
ned
.
RE
S
ET
V
OUT
SEN
S
E
t
d
t
t
d
1
...
2
3
4
5
6
...
...
19
