Datasheet

TPS3123-xx
TPS3124-xx, TPS3125-xx
TPS3126-xx, TPS3128-xx
SLVS227E –AUGUST 1999– REVISED AUGUST 2011 www.ti.com
RECOMMENDED OPERATING CONDITIONS
at specified temperature range.
MIN MAX UNIT
T
A
= 0°C to +85°C 0.75 3.3
V
DD
Supply voltage V
T
A
= –40°C to +85°C 0.85 3.3
V
DD
Manual reset voltage 0.0 V
DD
+0.3 V
V
WD1
Watchdog input voltage 0 V
DD
+0.3 V
V
IH
High-level input voltage 0.7×V
DD
V
V
IL
Low-level input voltage 0.3×V
DD
V
Δ t/ΔV Input transition rise and fall rate at WDI 1 μs/V
T
A
Operating free-air temperature range 40 +85 °C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MR pullup resistor (internal) 27 kΩ
WDI WDI = V
DD
= 3.3 V 1 1
I
IH
High-level input current μA
MR MR = 0.7 × V
DD
, V
DD
= 3.3 V 20 55
WDI WDI = 0 V, V
DD
= 3.3 V 1 1
I
IL
Low-level input current μA
MR MR = 0 V, V
DD
= 3.3 V 80 170
High-level output current TPS3126-xx,
I
OH
V
DD
= V
OH
= 3.3 V 200 nA
(leakage into RESET pin) TPS3128-xx
V
DD
= 1.5 V, I
OH
= –1 mA
RESET
V
DD
= 3.3 V, I
OH
= –4.5 mA
High-level output voltage
V
OH
0.8×V
DD
V
(TPS3123/4/5 only)
V
DD
= 0.75 V, I
OH
= –8 μA
RESET
V
DD
= 1.5 V, I
OH
= –1 mA
V
DD
= 0.75 V, I
OL
= 15 μA
RESET
V
DD
= 1.5 V, I
OL
= 1.4 mA 0.2 × V
DD
V
OL
Low-level output voltage V
V
DD
= 1.5 V, I
OL
= 1.4 mA
RESET
V
DD
= 3.3 V, I
OL
= 3 mA 0.4
TPS312xJ12 1.04 1.08 1.12
TPS312xG15 1.35 1.40 1.45
TPS312xJ18 1.56 1.62 1.68
Negative-going input threshold
V
IT–
TPS312xL30 T
A
= –40°C to +85°C 2.57 2.64 2.71 V
voltage
(1)
TPS312xE12 1.10 1.14 1.18
TPS312xE15 1.38 1.43 1.48
TPS312xE18 1.65 1.71 1.77
1 V < V
IT–
< 1.4 V 15
V
hys
Hysteresis at V
DD
input 1.4 V < V
IT–
< 2 V 20 mV
2 V < V
IT–
< 3 V 30
TPS3123-xx V
DD
= 0.75 V 14
WDI = V
DD
,
TPS3124-xx
MR unconnected
V
DD
= 3.3 V 22 30
TPS3128-xx
I
DD
Supply current μA
V
DD
= 0.75 V 14
TPS3125-xx
MR unconnected
TPS3126-xx
(2)
V
DD
= 3.3 V 18 25
C
i
Input capacitance at MR, WDI V
I
= 0 V to 3.3 V 5 pF
(1) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminal.
(2) The supply current during delay time t
d
is typical 5 μA higher.
6 Copyright © 1999–2011, Texas Instruments Incorporated