Datasheet
SLVS367A − MARCH 2001 − REVISED JUNE 2001
16
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VIN
GND
ENABLE
PWRRDY
SYNC
BOOT
HIGHDR
BOOTLO
VDRV
LOWDR
NC
PGND
U1
TPS2838
J1
J3
ENABLE
IN
PWRRDY
DELAY
SYNC
ADJ
DT
AGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C2
100 µF
++
C4
100 µF
R19
10 kΩ
R20
10 kΩ
R23
10 kΩ
C6
0.22 µF
Q1
IRF7201
VIN
C3
1 µF
Vphase
See Note A
L2
10 µH
L1
10 µH
BOOST
5 V
3.3 V LOGIC
J3
LOGIC GND
ANALOG GND
3.3 V ANALOG
3.3 V
+
C15
10 µF
C13
10 µF
+
C12
220 µF
R2
4.7 Ω
R4
4.7 Ω
C8
1000 pF
C28
1 µF
C1
1 µF
R22
165 kΩ
R21
30 kΩ
R24
10 Ω
V
CC
FB
COMP
DTC
GND
OUT
SCP
1
2
5
8
6
3
4
RT
7
C7
0.1 µF
U2
TL5001ACD
R1
1 kΩ
+
C5
1 µF
R3
13.7 kΩ
f
OSC
= 400 kHz
R18
0 Ω
R5
27.4 kΩ
C9
0.018 µF
R6
3.01 kΩ
R7
1 kΩ
R9
2.32 kΩ
C14
0.018 µF
R8
100 Ω
C11
390 pF
4.5 V − 8 V
1
2
1
2
3
C10
0.1 µF
1
2
3
4
5
6
Vfb
See Note B
NOTES: A. Node Vphase generates RFI. Make this as contained as possible.
B. Node Vphase is very sensitive. Make this as short as possible.
Figure 22. 3.3-V 3-A Synchronous-Buck Converter Circuit